10-Bit Flash ADCs and Beyond: An Automated Framework for TIQ Flash ADCs Design

Abdulrahman Abumurad, Ali Ozdemir, Kyusun Choi

Research output: Contribution to journalArticle

Abstract

In this work we introduce the flash ADC design automation (FADA) framework. It aims to reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes the selected TIQ comparators of the flash ADC for differential nonlinearity (DNL), integral nonlinearity (INL), analog voltage range, power consumption and comparator noise values. We performed a survey study on flash ADCs published in the last two decades and compared them to our 10-bit single-channel TIQ flash ADC. Further, it took FADA < 6 h to design the 10-bit TIQ flash ADC compared to few weeks of manual design. Accordingly, FADA selected TIQ comparators set for the 10-bit TIQ flash ADC with DNL and INL values less than 0.17 LSB and 0.16 LSB, respectively, when designed in the ibm65n CMOS technology. The 10-bit TIQ flash ADC has simulated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) values of 57.2 dBs and 61 dBs, respectively. It consumes 1.67 mW of power and operates at 1.57 GSample/s. FADA provides TIQ models to optimize for high-performance versus low-noise TIQ flash ADCs designs.

Original languageEnglish (US)
Pages (from-to)4314-4330
Number of pages17
JournalCircuits, Systems, and Signal Processing
Volume38
Issue number9
DOIs
StatePublished - Sep 15 2019

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Inverter
Flash
Quantization
Design Automation
Automation
Nonlinearity
Framework
Design
Optimise
Electric power utilization
Dynamic Range
Power Consumption
Electric potential
High Performance
Voltage
Analogue

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Applied Mathematics

Cite this

@article{5fd5e68fc2f74ae0a871a6c9dc529ff0,
title = "10-Bit Flash ADCs and Beyond: An Automated Framework for TIQ Flash ADCs Design",
abstract = "In this work we introduce the flash ADC design automation (FADA) framework. It aims to reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes the selected TIQ comparators of the flash ADC for differential nonlinearity (DNL), integral nonlinearity (INL), analog voltage range, power consumption and comparator noise values. We performed a survey study on flash ADCs published in the last two decades and compared them to our 10-bit single-channel TIQ flash ADC. Further, it took FADA < 6 h to design the 10-bit TIQ flash ADC compared to few weeks of manual design. Accordingly, FADA selected TIQ comparators set for the 10-bit TIQ flash ADC with DNL and INL values less than 0.17 LSB and 0.16 LSB, respectively, when designed in the ibm65n CMOS technology. The 10-bit TIQ flash ADC has simulated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) values of 57.2 dBs and 61 dBs, respectively. It consumes 1.67 mW of power and operates at 1.57 GSample/s. FADA provides TIQ models to optimize for high-performance versus low-noise TIQ flash ADCs designs.",
author = "Abdulrahman Abumurad and Ali Ozdemir and Kyusun Choi",
year = "2019",
month = "9",
day = "15",
doi = "10.1007/s00034-019-01024-1",
language = "English (US)",
volume = "38",
pages = "4314--4330",
journal = "Circuits, Systems, and Signal Processing",
issn = "0278-081X",
publisher = "Birkhause Boston",
number = "9",

}

10-Bit Flash ADCs and Beyond : An Automated Framework for TIQ Flash ADCs Design. / Abumurad, Abdulrahman; Ozdemir, Ali; Choi, Kyusun.

In: Circuits, Systems, and Signal Processing, Vol. 38, No. 9, 15.09.2019, p. 4314-4330.

Research output: Contribution to journalArticle

TY - JOUR

T1 - 10-Bit Flash ADCs and Beyond

T2 - An Automated Framework for TIQ Flash ADCs Design

AU - Abumurad, Abdulrahman

AU - Ozdemir, Ali

AU - Choi, Kyusun

PY - 2019/9/15

Y1 - 2019/9/15

N2 - In this work we introduce the flash ADC design automation (FADA) framework. It aims to reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes the selected TIQ comparators of the flash ADC for differential nonlinearity (DNL), integral nonlinearity (INL), analog voltage range, power consumption and comparator noise values. We performed a survey study on flash ADCs published in the last two decades and compared them to our 10-bit single-channel TIQ flash ADC. Further, it took FADA < 6 h to design the 10-bit TIQ flash ADC compared to few weeks of manual design. Accordingly, FADA selected TIQ comparators set for the 10-bit TIQ flash ADC with DNL and INL values less than 0.17 LSB and 0.16 LSB, respectively, when designed in the ibm65n CMOS technology. The 10-bit TIQ flash ADC has simulated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) values of 57.2 dBs and 61 dBs, respectively. It consumes 1.67 mW of power and operates at 1.57 GSample/s. FADA provides TIQ models to optimize for high-performance versus low-noise TIQ flash ADCs designs.

AB - In this work we introduce the flash ADC design automation (FADA) framework. It aims to reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes the selected TIQ comparators of the flash ADC for differential nonlinearity (DNL), integral nonlinearity (INL), analog voltage range, power consumption and comparator noise values. We performed a survey study on flash ADCs published in the last two decades and compared them to our 10-bit single-channel TIQ flash ADC. Further, it took FADA < 6 h to design the 10-bit TIQ flash ADC compared to few weeks of manual design. Accordingly, FADA selected TIQ comparators set for the 10-bit TIQ flash ADC with DNL and INL values less than 0.17 LSB and 0.16 LSB, respectively, when designed in the ibm65n CMOS technology. The 10-bit TIQ flash ADC has simulated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) values of 57.2 dBs and 61 dBs, respectively. It consumes 1.67 mW of power and operates at 1.57 GSample/s. FADA provides TIQ models to optimize for high-performance versus low-noise TIQ flash ADCs designs.

UR - http://www.scopus.com/inward/record.url?scp=85073644808&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85073644808&partnerID=8YFLogxK

U2 - 10.1007/s00034-019-01024-1

DO - 10.1007/s00034-019-01024-1

M3 - Article

AN - SCOPUS:85073644808

VL - 38

SP - 4314

EP - 4330

JO - Circuits, Systems, and Signal Processing

JF - Circuits, Systems, and Signal Processing

SN - 0278-081X

IS - 9

ER -