TY - JOUR
T1 - 2-D Strain FET (2D-SFET) Based SRAMs - Part I
T2 - Device-Circuit Interactions
AU - Thakuria, Niharika
AU - Schulman, Daniel
AU - Das, Saptarshi
AU - Gupta, Sumeet Kumar
N1 - Funding Information:
Manuscript received July 20, 2020; revised August 25, 2020; accepted September 1, 2020. Date of publication September 25, 2020; date of current version October 22, 2020. This work was supported in part by NSF under Grant 1640020, in part by Nanoelectronics Research Corporation (NERC), and in part by Semiconductor Research Corporation (SRC) under Grant 2699.003. The review of this article was arranged by Editor J. Kang. (Corresponding author: Niharika Thakuria.) Niharika Thakuria and Sumeet Kumar Gupta are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA (e-mail: nthakuri@purdue.edu; guptask@purdue.edu).
Publisher Copyright:
© 1963-2012 IEEE.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2020/11
Y1 - 2020/11
N2 - In this article, we analyze the characteristics of a recently conceived steep switching device 2-D Strain FET (2D-SFET) and present its circuit implications in the context of 6T-SRAM. We discuss the dependence of 2D-SFET characteristics on key design parameters, showing up to $2.7\times $ larger ON-current and 35% decrease in subthreshold swing when compared to 2D-FET. We analyze the performance of 2D-SFET (as drop-in replacement for standard 2D-FET) in 6T-SRAM for a range of design parameters and compare those to 2D-FET 6T-SRAM. 2D-SFET 6T-SRAM achieves up to 5.7% lower access time, 63% higher write margin, and comparable hold margin, but at the cost of comparable to 11% lower read stability and 16% increase in write time. In Part II of this article, we mitigate the read stability issues of 2D-SFET SRAMs by proposing ${V}_{{\mathrm {B}}}$ -enabled SRAM designs.
AB - In this article, we analyze the characteristics of a recently conceived steep switching device 2-D Strain FET (2D-SFET) and present its circuit implications in the context of 6T-SRAM. We discuss the dependence of 2D-SFET characteristics on key design parameters, showing up to $2.7\times $ larger ON-current and 35% decrease in subthreshold swing when compared to 2D-FET. We analyze the performance of 2D-SFET (as drop-in replacement for standard 2D-FET) in 6T-SRAM for a range of design parameters and compare those to 2D-FET 6T-SRAM. 2D-SFET 6T-SRAM achieves up to 5.7% lower access time, 63% higher write margin, and comparable hold margin, but at the cost of comparable to 11% lower read stability and 16% increase in write time. In Part II of this article, we mitigate the read stability issues of 2D-SFET SRAMs by proposing ${V}_{{\mathrm {B}}}$ -enabled SRAM designs.
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U2 - 10.1109/TED.2020.3022344
DO - 10.1109/TED.2020.3022344
M3 - Article
AN - SCOPUS:85094870215
VL - 67
SP - 4866
EP - 4874
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 11
M1 - 9205925
ER -