2007 IEEE device research conference: Tour de force multigate and nanowire metal oxide semiconductor field-effect transistors and their application

Pengpeng Zhang, Theresa S. Mayer, Thomas Nelson Jackson

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

Scaling of the conventional planar complementary metal oxide semiconductor (CMOS) faces many challenges. Top-down fabricated gate-all-around Si nanowire FinFETs, which are compatible with the CMOS processes, offer an opportunity to circumvent these limitations to boost the device scalability and performance. Beyond applications in CMOS technology, the thus fabricated Si nanowire arrays can be explored as biosensors, providing a possible route to multiplexed label-free electronic chips for molecular diagnostics.

Original languageEnglish (US)
Pages (from-to)6-9
Number of pages4
JournalACS nano
Volume1
Issue number1
DOIs
StatePublished - Aug 1 2007

Fingerprint

MOSFET devices
metal oxide semiconductors
Nanowires
CMOS
nanowires
field effect transistors
Metals
chips (electronics)
acceleration (physics)
bioinstrumentation
Biosensors
Scalability
Labels
routes
scaling
Oxide semiconductors

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Engineering(all)
  • Physics and Astronomy(all)

Cite this

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2007 IEEE device research conference : Tour de force multigate and nanowire metal oxide semiconductor field-effect transistors and their application. / Zhang, Pengpeng; Mayer, Theresa S.; Jackson, Thomas Nelson.

In: ACS nano, Vol. 1, No. 1, 01.08.2007, p. 6-9.

Research output: Contribution to journalArticle

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