24-bit significand multiplier for FPGA floating-point multiplication

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

This paper presents a 24-bit significand multiplier for single-precision floating-point multiplication that is optimized for Xilinx FPGAs with 6-input LUTs. The design combines a 24 × 7 LUT-based multiplier and one embedded multiplier to implement a 24 × 24 unsigned multiplier. The proposed design uses 35% fewer LUTs and is 1.11 times faster than a LogiCORE multiplier that also uses one embedded multiplier. A truncated- matrix version that allows faithful rounding uses 78% fewer LUTs and is 1.17 times faster than a LogiCORE multiplier that uses one embedded multiplier. Both designs are comparable in speed to a LogiCORE multiplier that uses two embedded multipliers.

Original languageEnglish (US)
Title of host publicationConference Record of the 49th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015
EditorsMichael B. Matthews
PublisherIEEE Computer Society
Pages717-721
Number of pages5
ISBN (Electronic)9781467385763
DOIs
StatePublished - Feb 26 2016
Event49th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 - Pacific Grove, United States
Duration: Nov 8 2015Nov 11 2015

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
Volume2016-February
ISSN (Print)1058-6393

Other

Other49th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015
CountryUnited States
CityPacific Grove
Period11/8/1511/11/15

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All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

Cite this

Walters, III, E. G. (2016). 24-bit significand multiplier for FPGA floating-point multiplication. In M. B. Matthews (Ed.), Conference Record of the 49th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 (pp. 717-721). [7421227] (Conference Record - Asilomar Conference on Signals, Systems and Computers; Vol. 2016-February). IEEE Computer Society. https://doi.org/10.1109/ACSSC.2015.7421227