The unprecedented technological success of the electronics industry over the last five decades have been driven by Silicon (Si) technology at the center of which resides the metal oxide semiconductor field effect transistor (MOSFET). Relentless scaling of MOSFET dimensions ensured faster and cheaper computing since more and more transistor could be packed into the same chip area.1 At the same time scaling of supply voltage (VDD) kept the power density practically constant. This golden era of MOSFET scaling often referred to as the Dennard Scaling era had continued for almost three decades. However, around 2005, the voltage scaling ended owing to the fact that further reduction in supply voltage (VDD) resulted in exponential increase in the OFF state current (IOFF) and hence the static power dissipation of the MOSFET. This was a direct consequence of non-scalability of the subthreshold slope (SS) to below 60mV/decade. Note, subthreshold slope is defined as the amount of gate voltage required to change the source to drain current of a MOSFET by one order of magnitude. The non-scalability of SS is the outcome of Boltzmann statistics, the governing physical principle for top of the barrier devices like MOSFETs. Although voltage scaling stopped, length scaling still continued for another decade albeit with new challenges like increasing power density, short channel effects and increasing parasitic. Unfortunately, even for the most advanced FinFET technology length scaling seems extremely challenging. Therefore, it is imminent that both aspects of MOSFET scaling will end very shortly. In order to sustain the growth of the semiconductor industry, it is necessary that novel low power beyond Boltzmann device concepts based on aggressively scalable materials be conceived immediately.