A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology

Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

39 Citations (Scopus)

Abstract

CMOS technology scaling continues to drive higher levels of integration in VLSI design, which adds more compute engines on a die. To meet the overall performance-scaling needs, high-speed and high-bandwidth memory is becoming increasingly important. Conventional VLSI systems often rely on on-die SRAMs to address the performance gap between CPU and main memory, DRAM. However, with the rapid growth in capacity needs for high-performance memory, SRAM is not always sufficient to meet the demands of bandwidth-intense applications. Embedded DRAM (eDRAM) has been explored as an alternative to satisfy the high-performance and density needs in memory [1-3]. In this paper, a high-performance eDRAM based on a 22nm tri-gate CMOS technology is introduced. This eDRAM technology enables the integration of an eDRAM cell into the logic technology platform [4]. The design features a well-balanced configuration to achieve both optimal array efficiency and bandwidth. By leveraging the high-performance and low-voltage tri-gate transistor at 22nm generation, the eDRAM achieves a wide range in operating voltage, from 1.1V down to 0.7V, which is essential for low-power logic applications.

Original languageEnglish (US)
Title of host publication2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages230-231
Number of pages2
ISBN (Print)9781479909186
DOIs
StatePublished - Jan 1 2014
Event2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014 - San Francisco, CA, United States
Duration: Feb 9 2014Feb 13 2014

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume57
ISSN (Print)0193-6530

Other

Other2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014
CountryUnited States
CitySan Francisco, CA
Period2/9/142/13/14

Fingerprint

Dynamic random access storage
Data storage equipment
Static random access storage
Bandwidth
Electric potential
Program processors
Transistors
Engines

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Hamzaoglu, F., Arslan, U., Bisnik, N., Ghosh, S., Lal, M. B., Lindert, N., ... Zhang, K. (2014). A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. In 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers (pp. 230-231). [6757412] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 57). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2014.6757412
Hamzaoglu, Fatih ; Arslan, Umut ; Bisnik, Nabhendra ; Ghosh, Swaroop ; Lal, Manoj B. ; Lindert, Nick ; Meterelliyoz, Mesut ; Osborne, Randy B. ; Park, Joodong ; Tomishima, Shigeki ; Wang, Yih ; Zhang, Kevin. / A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 230-231 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).
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Hamzaoglu, F, Arslan, U, Bisnik, N, Ghosh, S, Lal, MB, Lindert, N, Meterelliyoz, M, Osborne, RB, Park, J, Tomishima, S, Wang, Y & Zhang, K 2014, A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. in 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers., 6757412, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 57, Institute of Electrical and Electronics Engineers Inc., pp. 230-231, 2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014, San Francisco, CA, United States, 2/9/14. https://doi.org/10.1109/ISSCC.2014.6757412

A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. / Hamzaoglu, Fatih; Arslan, Umut; Bisnik, Nabhendra; Ghosh, Swaroop; Lal, Manoj B.; Lindert, Nick; Meterelliyoz, Mesut; Osborne, Randy B.; Park, Joodong; Tomishima, Shigeki; Wang, Yih; Zhang, Kevin.

2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. p. 230-231 6757412 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 57).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Hamzaoglu F, Arslan U, Bisnik N, Ghosh S, Lal MB, Lindert N et al. A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. In 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2014. p. 230-231. 6757412. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2014.6757412