A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

Saurabh Dighe, Sumeet Kumar Gupta, Vivek De, Sriram Vangal, Nitin Borkar, Shekhar Borkar, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured within-die core-to-core maximum operational frequency (Fmax), leakage & thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21% & chip energy by up to 14.5% across varying voltage/frequency (V/F) operating points & core counts.

Original languageEnglish (US)
Title of host publication2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
Pages250-251
Number of pages2
StatePublished - Sep 16 2011
Event2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan
Duration: Jun 15 2011Jun 17 2011

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2011 Symposium on VLSI Circuits, VLSIC 2011
CountryJapan
CityKyoto
Period6/15/116/17/11

Fingerprint

Scheduling
Electric potential
Voltage regulators
Energy efficiency
Rails
Industry

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Dighe, S., Gupta, S. K., De, V., Vangal, S., Borkar, N., Borkar, S., & Roy, K. (2011). A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping. In 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers (pp. 250-251). [5986132] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).
Dighe, Saurabh ; Gupta, Sumeet Kumar ; De, Vivek ; Vangal, Sriram ; Borkar, Nitin ; Borkar, Shekhar ; Roy, Kaushik. / A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping. 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers. 2011. pp. 250-251 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).
@inproceedings{73c98f63262648b8a7d204a0ab23ebe2,
title = "A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping",
abstract = "This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured within-die core-to-core maximum operational frequency (Fmax), leakage & thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21{\%} & chip energy by up to 14.5{\%} across varying voltage/frequency (V/F) operating points & core counts.",
author = "Saurabh Dighe and Gupta, {Sumeet Kumar} and Vivek De and Sriram Vangal and Nitin Borkar and Shekhar Borkar and Kaushik Roy",
year = "2011",
month = "9",
day = "16",
language = "English (US)",
isbn = "9784863481657",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
pages = "250--251",
booktitle = "2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers",

}

Dighe, S, Gupta, SK, De, V, Vangal, S, Borkar, N, Borkar, S & Roy, K 2011, A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping. in 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers., 5986132, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 250-251, 2011 Symposium on VLSI Circuits, VLSIC 2011, Kyoto, Japan, 6/15/11.

A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping. / Dighe, Saurabh; Gupta, Sumeet Kumar; De, Vivek; Vangal, Sriram; Borkar, Nitin; Borkar, Shekhar; Roy, Kaushik.

2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers. 2011. p. 250-251 5986132 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

AU - Dighe, Saurabh

AU - Gupta, Sumeet Kumar

AU - De, Vivek

AU - Vangal, Sriram

AU - Borkar, Nitin

AU - Borkar, Shekhar

AU - Roy, Kaushik

PY - 2011/9/16

Y1 - 2011/9/16

N2 - This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured within-die core-to-core maximum operational frequency (Fmax), leakage & thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21% & chip energy by up to 14.5% across varying voltage/frequency (V/F) operating points & core counts.

AB - This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured within-die core-to-core maximum operational frequency (Fmax), leakage & thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21% & chip energy by up to 14.5% across varying voltage/frequency (V/F) operating points & core counts.

UR - http://www.scopus.com/inward/record.url?scp=80052678519&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052678519&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:80052678519

SN - 9784863481657

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 250

EP - 251

BT - 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers

ER -

Dighe S, Gupta SK, De V, Vangal S, Borkar N, Borkar S et al. A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping. In 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers. 2011. p. 250-251. 5986132. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).