A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

Saurabh Dighe, Sumeet Kumar Gupta, Vivek De, Sriram Vangal, Nitin Borkar, Shekhar Borkar, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured within-die core-to-core maximum operational frequency (Fmax), leakage & thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21% & chip energy by up to 14.5% across varying voltage/frequency (V/F) operating points & core counts.

Original languageEnglish (US)
Title of host publication2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
Pages250-251
Number of pages2
StatePublished - Sep 16 2011
Event2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan
Duration: Jun 15 2011Jun 17 2011

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2011 Symposium on VLSI Circuits, VLSIC 2011
CountryJapan
CityKyoto
Period6/15/116/17/11

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Dighe, S., Gupta, S. K., De, V., Vangal, S., Borkar, N., Borkar, S., & Roy, K. (2011). A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping. In 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers (pp. 250-251). [5986132] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).