This paper presents the design and post-layout simulation results of a 64-channel wireless and implantable system-on-chip (SoC) for studying gastric electrophysiology. The SoC includes 64 time-multiplexed low-noise amplifiers (LNAs) followed by a 10-bit low-power successive approximation register (SAR) analog-to-digital converter (ADC), and a power management unit for recharging the SoC battery inductively and communicating with an external reader via load-shift keying (LSK) modulation of the receiver coil. The SoC has been designed in a 0.35 μm standard CMOS process, occupying 25 mm2. In post-layout simulations, each LNA achieved an adjustable gain of 40-52 dB, and an input-referred noise of 6 μVrms within the bandwidth of 10 mHz-2 Hz while consuming 40 nA from a single 2.5 V supply. Each channel was sampled at 244 Hz with 10 bits of resolution, leading to the net data rate of 156 kbps for recording 64 channels. The power management, operating at 13.56 MHz, recharged a 3.7 V battery with the adjustable current range of 0-15 mA while maintaining the rectifier voltage constant at 4.4 V.