Multiport memories are widely used in multi-processor systems, telecommunication ASICs etc. Research papers which define multi-port memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multi-port memories. In this paper, we discuss some basics about the architecture of two-port memories and fault models for the same. We have then used the serial testing mechanism to propose new algorithms which can prove effective to reduce the hardware cost considerably on a chip with many multi-port memories. Once the serial interfacing for two-port memory testing is understood, it can be extended for p-port memories (p>2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead and tolerable test application time.