A built-in self-testing method for embedded multiport memory arrays

V. Narayanan, S. Ghosh, W. B. Jone, S. R. Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multiport memories are widely used in multi-processor systems, telecommunication ASICs etc. Research papers which define multi-port memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multi-port memories. In this paper, we discuss some basics about the architecture of two-port memories and fault models for the same. We have then used the serial testing mechanism to propose new algorithms which can prove effective to reduce the hardware cost considerably on a chip with many multi-port memories. Once the serial interfacing for two-port memory testing is understood, it can be extended for p-port memories (p>2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead and tolerable test application time.

Original languageEnglish (US)
Title of host publicationProceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04
EditorsS. Demidenko, R. Ottoboni, D. Petri, V. Piuri, D.C.T. Weng
Pages2027-2032
Number of pages6
DOIs
StatePublished - Oct 8 2004
EventProceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04 - Como, Italy
Duration: May 18 2004May 20 2004

Publication series

NameConference Record - IEEE Instrumentation and Measurement Technology Conference
Volume3
ISSN (Print)1091-5281

Other

OtherProceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04
CountryItaly
CityComo
Period5/18/045/20/04

Fingerprint

Data storage equipment
Testing
Hardware
Telecommunication systems
Application specific integrated circuits
Costs

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Narayanan, V., Ghosh, S., Jone, W. B., & Das, S. R. (2004). A built-in self-testing method for embedded multiport memory arrays. In S. Demidenko, R. Ottoboni, D. Petri, V. Piuri, & D. C. T. Weng (Eds.), Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04 (pp. 2027-2032). (Conference Record - IEEE Instrumentation and Measurement Technology Conference; Vol. 3). https://doi.org/10.1109/IMTC.2004.1351487
Narayanan, V. ; Ghosh, S. ; Jone, W. B. ; Das, S. R. / A built-in self-testing method for embedded multiport memory arrays. Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04. editor / S. Demidenko ; R. Ottoboni ; D. Petri ; V. Piuri ; D.C.T. Weng. 2004. pp. 2027-2032 (Conference Record - IEEE Instrumentation and Measurement Technology Conference).
@inproceedings{45579999fd3a4a60bffa21c3753c373b,
title = "A built-in self-testing method for embedded multiport memory arrays",
abstract = "Multiport memories are widely used in multi-processor systems, telecommunication ASICs etc. Research papers which define multi-port memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multi-port memories. In this paper, we discuss some basics about the architecture of two-port memories and fault models for the same. We have then used the serial testing mechanism to propose new algorithms which can prove effective to reduce the hardware cost considerably on a chip with many multi-port memories. Once the serial interfacing for two-port memory testing is understood, it can be extended for p-port memories (p>2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead and tolerable test application time.",
author = "V. Narayanan and S. Ghosh and Jone, {W. B.} and Das, {S. R.}",
year = "2004",
month = "10",
day = "8",
doi = "10.1109/IMTC.2004.1351487",
language = "English (US)",
isbn = "078038248X",
series = "Conference Record - IEEE Instrumentation and Measurement Technology Conference",
pages = "2027--2032",
editor = "S. Demidenko and R. Ottoboni and D. Petri and V. Piuri and D.C.T. Weng",
booktitle = "Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04",

}

Narayanan, V, Ghosh, S, Jone, WB & Das, SR 2004, A built-in self-testing method for embedded multiport memory arrays. in S Demidenko, R Ottoboni, D Petri, V Piuri & DCT Weng (eds), Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04. Conference Record - IEEE Instrumentation and Measurement Technology Conference, vol. 3, pp. 2027-2032, Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04, Como, Italy, 5/18/04. https://doi.org/10.1109/IMTC.2004.1351487

A built-in self-testing method for embedded multiport memory arrays. / Narayanan, V.; Ghosh, S.; Jone, W. B.; Das, S. R.

Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04. ed. / S. Demidenko; R. Ottoboni; D. Petri; V. Piuri; D.C.T. Weng. 2004. p. 2027-2032 (Conference Record - IEEE Instrumentation and Measurement Technology Conference; Vol. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A built-in self-testing method for embedded multiport memory arrays

AU - Narayanan, V.

AU - Ghosh, S.

AU - Jone, W. B.

AU - Das, S. R.

PY - 2004/10/8

Y1 - 2004/10/8

N2 - Multiport memories are widely used in multi-processor systems, telecommunication ASICs etc. Research papers which define multi-port memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multi-port memories. In this paper, we discuss some basics about the architecture of two-port memories and fault models for the same. We have then used the serial testing mechanism to propose new algorithms which can prove effective to reduce the hardware cost considerably on a chip with many multi-port memories. Once the serial interfacing for two-port memory testing is understood, it can be extended for p-port memories (p>2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead and tolerable test application time.

AB - Multiport memories are widely used in multi-processor systems, telecommunication ASICs etc. Research papers which define multi-port memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multi-port memories. In this paper, we discuss some basics about the architecture of two-port memories and fault models for the same. We have then used the serial testing mechanism to propose new algorithms which can prove effective to reduce the hardware cost considerably on a chip with many multi-port memories. Once the serial interfacing for two-port memory testing is understood, it can be extended for p-port memories (p>2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead and tolerable test application time.

UR - http://www.scopus.com/inward/record.url?scp=4644234022&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=4644234022&partnerID=8YFLogxK

U2 - 10.1109/IMTC.2004.1351487

DO - 10.1109/IMTC.2004.1351487

M3 - Conference contribution

AN - SCOPUS:4644234022

SN - 078038248X

T3 - Conference Record - IEEE Instrumentation and Measurement Technology Conference

SP - 2027

EP - 2032

BT - Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04

A2 - Demidenko, S.

A2 - Ottoboni, R.

A2 - Petri, D.

A2 - Piuri, V.

A2 - Weng, D.C.T.

ER -

Narayanan V, Ghosh S, Jone WB, Das SR. A built-in self-testing method for embedded multiport memory arrays. In Demidenko S, Ottoboni R, Petri D, Piuri V, Weng DCT, editors, Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04. 2004. p. 2027-2032. (Conference Record - IEEE Instrumentation and Measurement Technology Conference). https://doi.org/10.1109/IMTC.2004.1351487