With recent advances in semiconductor technologies, the design and use of memories for realizing complex system-on-a-chip (SoC) is very widespread. The growing need for storage in computer, communication, and network appliances has motivated new advancements in faster and more efficient ways to test memories. Efficient testing schemes for single-port memories have been readily available. Multiport memories are widely used in multiprocessor systems, telecommunication application-specific integrated circuits (ASICs), etc. Research papers which define multiport memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multiport memories. In this paper, we develop a powerful test architecture for two-port memories using the serial interfacing technique. Based on the serial testing mechanism, we propose new march algorithms which can prove effective to reduce hardware cost considerably for a chip with many two-port memories. Once we understand how serial interfacing helps test two-port memories, one possible extension is to use serial interfacing for p-port memories (p > 2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, iow hardware overhead, and tolerable test application time.
|Original language||English (US)|
|Number of pages||18|
|Journal||IEEE Transactions on Instrumentation and Measurement|
|State||Published - Oct 2005|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering