Abstract
In this paper we present a cache coherence protocol for multistage interconnection network (MIN)-based multiprocessors with two distinct private caches:privateblocks caches (PCache) containing blocks private to a process and shared-blocks caches (SCache) containing data accessible by all processes. The architecture is extended by a coherence control bus connecting all shared-block cache controllers. Timing problems due to variable transit delays through the MIN are dealt with by introducing Transient states in the proposed cache coherence protocol. The impact of the coherence protocol on system performance is evaluated through a performance study of three phases. Assuming homogeneity of all nodes, a single-node queuing model (phase 3) is developed to analyze system performance. This model is solved for processor and coherence bus utilizations using the mean value analysis (MVA) technique with shared-blocks steady state probabilities (phase 1) and communication delays (phase 2) as input parameters. The performance of our system is compared to that of a system with an equivalent-sized unified cache and with a multiprocessor implementing a directory-based coherence protocol. System performance measures are verified through simulation.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 163-185 |
| Number of pages | 23 |
| Journal | The Journal of Supercomputing |
| Volume | 8 |
| Issue number | 2 |
| DOIs | |
| State | Published - Jun 1 1994 |
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All Science Journal Classification (ASJC) codes
- Software
- Theoretical Computer Science
- Information Systems
- Hardware and Architecture
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A Cache coherence protocol for MIN-based multiprocessors. / Yousif, Mazin S.; Das, Chita R.; Thazhuthaveetil, Matthew J.
In: The Journal of Supercomputing, Vol. 8, No. 2, 01.06.1994, p. 163-185.Research output: Contribution to journal › Article
TY - JOUR
T1 - A Cache coherence protocol for MIN-based multiprocessors
AU - Yousif, Mazin S.
AU - Das, Chita R.
AU - Thazhuthaveetil, Matthew J.
PY - 1994/6/1
Y1 - 1994/6/1
N2 - In this paper we present a cache coherence protocol for multistage interconnection network (MIN)-based multiprocessors with two distinct private caches:privateblocks caches (PCache) containing blocks private to a process and shared-blocks caches (SCache) containing data accessible by all processes. The architecture is extended by a coherence control bus connecting all shared-block cache controllers. Timing problems due to variable transit delays through the MIN are dealt with by introducing Transient states in the proposed cache coherence protocol. The impact of the coherence protocol on system performance is evaluated through a performance study of three phases. Assuming homogeneity of all nodes, a single-node queuing model (phase 3) is developed to analyze system performance. This model is solved for processor and coherence bus utilizations using the mean value analysis (MVA) technique with shared-blocks steady state probabilities (phase 1) and communication delays (phase 2) as input parameters. The performance of our system is compared to that of a system with an equivalent-sized unified cache and with a multiprocessor implementing a directory-based coherence protocol. System performance measures are verified through simulation.
AB - In this paper we present a cache coherence protocol for multistage interconnection network (MIN)-based multiprocessors with two distinct private caches:privateblocks caches (PCache) containing blocks private to a process and shared-blocks caches (SCache) containing data accessible by all processes. The architecture is extended by a coherence control bus connecting all shared-block cache controllers. Timing problems due to variable transit delays through the MIN are dealt with by introducing Transient states in the proposed cache coherence protocol. The impact of the coherence protocol on system performance is evaluated through a performance study of three phases. Assuming homogeneity of all nodes, a single-node queuing model (phase 3) is developed to analyze system performance. This model is solved for processor and coherence bus utilizations using the mean value analysis (MVA) technique with shared-blocks steady state probabilities (phase 1) and communication delays (phase 2) as input parameters. The performance of our system is compared to that of a system with an equivalent-sized unified cache and with a multiprocessor implementing a directory-based coherence protocol. System performance measures are verified through simulation.
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U2 - 10.1007/BF01204660
DO - 10.1007/BF01204660
M3 - Article
AN - SCOPUS:0028442777
VL - 8
SP - 163
EP - 185
JO - Journal of Supercomputing
JF - Journal of Supercomputing
SN - 0920-8542
IS - 2
ER -