A Cache Coherence Protocol for MIN-Based Multiprocessors with Limited Inclusion

Mazin S. Yousif, Chita R. Das, Matthew J. Thazhuthaveetil

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

In this paper, we look into a feasible approach to incorporating caches into selected switching ele ments of a multistage interconnection network (MIN)- based multiprocessor. Along with the processor private caches, these switch caches form a two-level cache hi erarchy. Selected switch caches within a particular stage of the MIN are connected by a coherence con trol bus, through which a write-invalidate cache coher ence protocol is maintained. Considering scalability and practicality issues, only limited inclusion between the two cache levels is enforced. A simulation-based performance study is conducted to analyze the impact of the protocol on system performance. Comparison between limited and strict inclusion shows that system performance declines with limited inclusion.

Original languageEnglish (US)
Title of host publicationArchitecture
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages254-257
Number of pages4
ISBN (Electronic)0849389836
DOIs
StatePublished - Jan 1 1993
Event1993 International Conference on Parallel Processing, ICPP 1993 - Syracuse, United States
Duration: Aug 16 1993Aug 20 1993

Publication series

NameProceedings of the International Conference on Parallel Processing
Volume1
ISSN (Print)0190-3918

Conference

Conference1993 International Conference on Parallel Processing, ICPP 1993
CountryUnited States
CitySyracuse
Period8/16/938/20/93

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All Science Journal Classification (ASJC) codes

  • Software
  • Mathematics(all)
  • Hardware and Architecture

Cite this

Yousif, M. S., Das, C. R., & Thazhuthaveetil, M. J. (1993). A Cache Coherence Protocol for MIN-Based Multiprocessors with Limited Inclusion. In Architecture (pp. 254-257). [4134149] (Proceedings of the International Conference on Parallel Processing; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.1993.13