A Cache coherence protocol for MIN-based multiprocessors

Mathematics

• Cache Coherence 100%
• Multistage Interconnection Networks 82%
• Cache 69%
• Multiprocessor 63%
• System Performance 37%
• Mean Value Analysis 16%
• Communication Delay 14%
• Queuing Model 14%
• Transient State 12%
• Variable Delay 11%
• Performance 11%
• Timing 11%
• Vertex of a graph 10%
• Performance Measures 10%
• Architecture 10%
• Homogeneity 9%
• Controller 8%
• Distinct 6%
• Simulation 5%
• Model 3%

Engineering & Materials Science

• Value engineering 9%
• Controllers 4%
• Communication 3%