A case for heterogeneous on-chip interconnects for CMPs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

86 Scopus citations

Abstract

Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the entire network. While this homogeneous network design eases the burden on a network designer, partitioning the resources equally among all routers across the network does not lead to optimal resource usage, and hence, affects the performance-power envelope. In this work, we propose to apportion the resources in an NoC to leverage the non-uniformity in network resource demand. Our proposal includes partitioning the network resources, specifically buffers and links, in an optimal manner. This approach results in redistributing resources such that routers that require more resources are allocated more buffers and wider links compared to routers demanding fewer resources. This results in a novel heterogeneous network, called HeteroNoC, which is composed of two types of routers-small power efficient routers, and big high performance routers. We evaluate a number of heterogeneous network configurations, composed of big and small routers, and show that giving more resources to routers along the diagonals in a mesh network provides maximum benefits in terms of performance and power. We also show the potential benefits of the HeteroNoC design by co-evaluating it with memory-controllers and configuring it with an asymmetric CMP consisting of heterogeneous cores.

Original languageEnglish (US)
Title of host publicationProceeding of the 38th Annual International Symposium on Computer Architecture, ISCA'11
Pages389-399
Number of pages11
DOIs
StatePublished - Sep 13 2011
Event38th Annual International Symposium on Computer Architecture, ISCA'11 - San Jose, CA, United States
Duration: Jun 4 2011Jun 8 2011

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

Other38th Annual International Symposium on Computer Architecture, ISCA'11
CountryUnited States
CitySan Jose, CA
Period6/4/116/8/11

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Mishra, A. K., Narayanan, V., & Das, C. (2011). A case for heterogeneous on-chip interconnects for CMPs. In Proceeding of the 38th Annual International Symposium on Computer Architecture, ISCA'11 (pp. 389-399). (Proceedings - International Symposium on Computer Architecture). https://doi.org/10.1145/2000064.2000111