A case for integrated processor-cache partitioning in chip multiprocessors

Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

Existing cache partitioning schemes are designed in a manner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an operating system directed integrated processor-cache partitioning scheme that partitions both the available processors and the shared cache in a chip multiprocessor among different multi-threaded applications. Extensive simulations using a set of multiprogrammed workloads show that our integrated processor-cache partitioning scheme facilitates achieving better performance isolation as compared to state of the art hardware/software based solutions. Specifically, our integrated processor-cache partitioning approach performs, on an average, 20.83% and 14.14% better than equal partitioning and the implicit partitioning enforced by the underlying operating system, respectively, on the fair speedup metric on an 8 core system. We also compare our approach to processor partitioning alone and a state-of-the-art cache partitioning scheme and our scheme fares 8.21% and 9.19% better than these schemes on a 16 core system.

Original languageEnglish (US)
Title of host publicationProceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC '09
DOIs
StatePublished - Dec 1 2009
EventConference on High Performance Computing Networking, Storage and Analysis, SC '09 - Portland, OR, United States
Duration: Nov 14 2009Nov 20 2009

Publication series

NameProceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC '09

Other

OtherConference on High Performance Computing Networking, Storage and Analysis, SC '09
CountryUnited States
CityPortland, OR
Period11/14/0911/20/09

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Computer Science Applications

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    Srikantaiah, S., Das, R., Mishra, A. K., Das, C. R., & Kandemir, M. (2009). A case for integrated processor-cache partitioning in chip multiprocessors. In Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC '09 [1654066] (Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC '09). https://doi.org/10.1145/1654059.1654066