A clock power model to evaluate impact of architectural and technology optimizations - A summary

David E. Duarte, N. Vijaykrishnan, Mary Jane Irwin

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of existing microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock generation and distribution circuitry, including both the dynamic and leakage power components. The validation results show that the model is reasonably accurate, with the average deviation being within 10% of SPICE simulations. Access to this model can enable further research at high-level design stages in optimizing the system clock power. To illustrate this, a few architectural modifications are considered and their effect on the clock sub-system and the total system power budget is assessed.

Original languageEnglish (US)
Pages (from-to)36-39
Number of pages4
JournalIEEE Circuits and Systems Magazine
Volume3
Issue number3
DOIs
StatePublished - Jan 1 2003

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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