TY - JOUR
T1 - A compiler-based approach for dynamically managing scratch-pad memories in embedded systems
AU - Kandemir, Mahmut
AU - Ramanujam, J.
AU - Irwin, Mary Jane
AU - Vijaykrishnan, N.
AU - Kadayif, Ismail
AU - Parikh, Amisha
N1 - Funding Information:
Manuscript received July 5, 2001; revised April 29, 2003. A preliminary version of this paper appeared in the Proceedings of the 38th Design Automation Conference (DAC’01) Las Vegas, NV, June 2001, pp. 690-695. This work was supported in part by the Pittsburgh Digital Greenhouse through a grant from the Department of Community and Economic Development, Commonwealth of Pennsylvania, and in part by the National Science Foundation (NSF) under CAREER Awards 0093082 and 0093085. The work of J. Ramanujam was supported in part by the NSF under Grant CCR-0073800 and in part by the NSF under Young Investigator Award CCR-9457768. This paper was recommended by Associate Editor R. Gupta.
PY - 2004/2
Y1 - 2004/2
N2 - Optimizations aimed at improving the efficiency of on-chip memories in embedded systems are extremely important. Using a suitable combination of program transformations and memory design space exploration aimed at enhancing data locality enables significant reductions in effective memory access latencies. While numerous compiler optimizations have been proposed to improve cache performance, there are relatively few techniques that focus on software-managed on-chip memories. It is well-known that software-managed memories are important in real-time embedded environments with hard deadlines as they allow one to accurately predict the amount of time a given code segment will take. In this paper, we propose and evaluate a compiler-controlled dynamic on-chip scratch-pad memory (SPM) management framework. Our framework includes an optimization suite that uses loop and data transformations, an on-chip memory, partitioning step, and a code-rewriting phase that collectively transform an input code automatically to take advantage of the on-chip SPM. Compared with previous work, the proposed scheme is dynamic, and allows the contents of the SPM to change during the course of execution, depending on the changes in the data access pattern. Experimental results from our implementation using a source-to-source translator and a generic cost model indicate significant reductions in data transfer activity between the SPM and off-chip memory.
AB - Optimizations aimed at improving the efficiency of on-chip memories in embedded systems are extremely important. Using a suitable combination of program transformations and memory design space exploration aimed at enhancing data locality enables significant reductions in effective memory access latencies. While numerous compiler optimizations have been proposed to improve cache performance, there are relatively few techniques that focus on software-managed on-chip memories. It is well-known that software-managed memories are important in real-time embedded environments with hard deadlines as they allow one to accurately predict the amount of time a given code segment will take. In this paper, we propose and evaluate a compiler-controlled dynamic on-chip scratch-pad memory (SPM) management framework. Our framework includes an optimization suite that uses loop and data transformations, an on-chip memory, partitioning step, and a code-rewriting phase that collectively transform an input code automatically to take advantage of the on-chip SPM. Compared with previous work, the proposed scheme is dynamic, and allows the contents of the SPM to change during the course of execution, depending on the changes in the data access pattern. Experimental results from our implementation using a source-to-source translator and a generic cost model indicate significant reductions in data transfer activity between the SPM and off-chip memory.
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U2 - 10.1109/TCAD.2003.822123
DO - 10.1109/TCAD.2003.822123
M3 - Article
AN - SCOPUS:1242286076
VL - 23
SP - 243
EP - 260
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 2
ER -