A PLL power model that accurately estimates the power consumption during both lock and acquisition states is presented. The model is within 5% of circuit level simulation (SPICE) values. No significant power overhead (+/-5% of the power consumed at the final frequency) is incurred during the acquisition process.
|Original language||English (US)|
|Number of pages||1|
|Journal||Proceedings -Design, Automation and Test in Europe, DATE|
|State||Published - Dec 1 2002|
|Event||2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France|
Duration: Mar 4 2002 → Mar 8 2002
All Science Journal Classification (ASJC) codes