A computationally efficient compact model for leakage in cross-point array

Ahmedullah Aziz, Nicholas Jao, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Cross-point architecture, while being appealing in consideration of high integration density, suffers from leakage through sneak paths across the array. The leakage current flowing through half-accessed and in some cases, unaccessed cells (and the corresponding leakage power) are important determinants of array performance. Proper estimation of these components is computationally challenging and often demands rigorous simulation efforts. This paper presents a computationally efficient compact model to assess the leakage in cross-point array employing threshold switch selectors. We provide closed form mathematical expressions that govern our model and explain the derivation methodologies. We analyze and verify the validity of the model by cross-checking with results from conventional rigorous array simulations. The model shows excellent matching (∼99% accuracy) with rigorous simulations for different array sizes (16×16 through 256×256). The model has been tested with various ranges of selector OFF resistance (0.1 ΜΩ to 1 ΟΩ), interconnect resistance (1 mΩ/□ to 10 Ω/□) and access voltage (0.2V to 1V). The test results from the model show accurate response in comparison with those obtained from intensive array simulations.

Original languageEnglish (US)
Title of host publication2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages141-144
Number of pages4
ISBN (Electronic)9784863486102
DOIs
StatePublished - Oct 25 2017
Event2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017 - Kamakura, Japan
Duration: Sep 7 2017Sep 9 2017

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume2017-September

Other

Other2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017
CountryJapan
CityKamakura
Period9/7/179/9/17

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Modeling and Simulation

Cite this

Aziz, A., Jao, N., Datta, S., Narayanan, V., & Gupta, S. K. (2017). A computationally efficient compact model for leakage in cross-point array. In 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017 (pp. 141-144). [8085284] (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2017-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/SISPAD.2017.8085284