A computationally efficient compact model for leakage in cross-point array

Ahmedullah Aziz, Nicholas Jao, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Cross-point architecture, while being appealing in consideration of high integration density, suffers from leakage through sneak paths across the array. The leakage current flowing through half-accessed and in some cases, unaccessed cells (and the corresponding leakage power) are important determinants of array performance. Proper estimation of these components is computationally challenging and often demands rigorous simulation efforts. This paper presents a computationally efficient compact model to assess the leakage in cross-point array employing threshold switch selectors. We provide closed form mathematical expressions that govern our model and explain the derivation methodologies. We analyze and verify the validity of the model by cross-checking with results from conventional rigorous array simulations. The model shows excellent matching (∼99% accuracy) with rigorous simulations for different array sizes (16×16 through 256×256). The model has been tested with various ranges of selector OFF resistance (0.1 ΜΩ to 1 ΟΩ), interconnect resistance (1 mΩ/□ to 10 Ω/□) and access voltage (0.2V to 1V). The test results from the model show accurate response in comparison with those obtained from intensive array simulations.

Original languageEnglish (US)
Title of host publication2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages141-144
Number of pages4
ISBN (Electronic)9784863486102
DOIs
StatePublished - Oct 25 2017
Event2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017 - Kamakura, Japan
Duration: Sep 7 2017Sep 9 2017

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume2017-September

Other

Other2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017
CountryJapan
CityKamakura
Period9/7/179/9/17

Fingerprint

Leakage
Selector
Simulation
Model
Leakage Current
Interconnect
Leakage currents
Switch
Determinant
Closed-form
Voltage
Switches
Verify
Path
Methodology
Cell
Electric potential
Range of data
Resistance

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Modeling and Simulation

Cite this

Aziz, A., Jao, N., Datta, S., Narayanan, V., & Gupta, S. K. (2017). A computationally efficient compact model for leakage in cross-point array. In 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017 (pp. 141-144). [8085284] (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2017-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/SISPAD.2017.8085284
Aziz, Ahmedullah ; Jao, Nicholas ; Datta, Suman ; Narayanan, Vijaykrishnan ; Gupta, Sumeet Kumar. / A computationally efficient compact model for leakage in cross-point array. 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 141-144 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).
@inproceedings{4f83dd33db234c0794a116cfcbb40abb,
title = "A computationally efficient compact model for leakage in cross-point array",
abstract = "Cross-point architecture, while being appealing in consideration of high integration density, suffers from leakage through sneak paths across the array. The leakage current flowing through half-accessed and in some cases, unaccessed cells (and the corresponding leakage power) are important determinants of array performance. Proper estimation of these components is computationally challenging and often demands rigorous simulation efforts. This paper presents a computationally efficient compact model to assess the leakage in cross-point array employing threshold switch selectors. We provide closed form mathematical expressions that govern our model and explain the derivation methodologies. We analyze and verify the validity of the model by cross-checking with results from conventional rigorous array simulations. The model shows excellent matching (∼99{\%} accuracy) with rigorous simulations for different array sizes (16×16 through 256×256). The model has been tested with various ranges of selector OFF resistance (0.1 ΜΩ to 1 ΟΩ), interconnect resistance (1 mΩ/□ to 10 Ω/□) and access voltage (0.2V to 1V). The test results from the model show accurate response in comparison with those obtained from intensive array simulations.",
author = "Ahmedullah Aziz and Nicholas Jao and Suman Datta and Vijaykrishnan Narayanan and Gupta, {Sumeet Kumar}",
year = "2017",
month = "10",
day = "25",
doi = "10.23919/SISPAD.2017.8085284",
language = "English (US)",
series = "International Conference on Simulation of Semiconductor Processes and Devices, SISPAD",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "141--144",
booktitle = "2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017",
address = "United States",

}

Aziz, A, Jao, N, Datta, S, Narayanan, V & Gupta, SK 2017, A computationally efficient compact model for leakage in cross-point array. in 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017., 8085284, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, vol. 2017-September, Institute of Electrical and Electronics Engineers Inc., pp. 141-144, 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017, Kamakura, Japan, 9/7/17. https://doi.org/10.23919/SISPAD.2017.8085284

A computationally efficient compact model for leakage in cross-point array. / Aziz, Ahmedullah; Jao, Nicholas; Datta, Suman; Narayanan, Vijaykrishnan; Gupta, Sumeet Kumar.

2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 141-144 8085284 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2017-September).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A computationally efficient compact model for leakage in cross-point array

AU - Aziz, Ahmedullah

AU - Jao, Nicholas

AU - Datta, Suman

AU - Narayanan, Vijaykrishnan

AU - Gupta, Sumeet Kumar

PY - 2017/10/25

Y1 - 2017/10/25

N2 - Cross-point architecture, while being appealing in consideration of high integration density, suffers from leakage through sneak paths across the array. The leakage current flowing through half-accessed and in some cases, unaccessed cells (and the corresponding leakage power) are important determinants of array performance. Proper estimation of these components is computationally challenging and often demands rigorous simulation efforts. This paper presents a computationally efficient compact model to assess the leakage in cross-point array employing threshold switch selectors. We provide closed form mathematical expressions that govern our model and explain the derivation methodologies. We analyze and verify the validity of the model by cross-checking with results from conventional rigorous array simulations. The model shows excellent matching (∼99% accuracy) with rigorous simulations for different array sizes (16×16 through 256×256). The model has been tested with various ranges of selector OFF resistance (0.1 ΜΩ to 1 ΟΩ), interconnect resistance (1 mΩ/□ to 10 Ω/□) and access voltage (0.2V to 1V). The test results from the model show accurate response in comparison with those obtained from intensive array simulations.

AB - Cross-point architecture, while being appealing in consideration of high integration density, suffers from leakage through sneak paths across the array. The leakage current flowing through half-accessed and in some cases, unaccessed cells (and the corresponding leakage power) are important determinants of array performance. Proper estimation of these components is computationally challenging and often demands rigorous simulation efforts. This paper presents a computationally efficient compact model to assess the leakage in cross-point array employing threshold switch selectors. We provide closed form mathematical expressions that govern our model and explain the derivation methodologies. We analyze and verify the validity of the model by cross-checking with results from conventional rigorous array simulations. The model shows excellent matching (∼99% accuracy) with rigorous simulations for different array sizes (16×16 through 256×256). The model has been tested with various ranges of selector OFF resistance (0.1 ΜΩ to 1 ΟΩ), interconnect resistance (1 mΩ/□ to 10 Ω/□) and access voltage (0.2V to 1V). The test results from the model show accurate response in comparison with those obtained from intensive array simulations.

UR - http://www.scopus.com/inward/record.url?scp=85039059196&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85039059196&partnerID=8YFLogxK

U2 - 10.23919/SISPAD.2017.8085284

DO - 10.23919/SISPAD.2017.8085284

M3 - Conference contribution

T3 - International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

SP - 141

EP - 144

BT - 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Aziz A, Jao N, Datta S, Narayanan V, Gupta SK. A computationally efficient compact model for leakage in cross-point array. In 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 141-144. 8085284. (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). https://doi.org/10.23919/SISPAD.2017.8085284