A crosstalk aware interconnect with variable cycle transmission

Lin Li, Vijaykrishnan Narayanan, Mahmut Kandemir, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

51 Citations (Scopus)

Abstract

Crosstalk between wires, caused by increased capacitive coupling, is considered one of the major factors that affect the performance of interconnects such as buses. The data-dependent nature of crosstalk-induced delays necessitates bus cycle time to be designed for the worst case crosstalk. However, this pessimism incurs a significant performance penalty. Consequently, we propose a crosstalk aware interconnect that uses a faster clock and dynamically controls the number of cycles required for transmission based on the estimated delay of the data pattern to be transmitted. In order to accomplish this, we designed a crosstalk analyzer circuit that is incorporated into the sender side of the bus and support a variable cycle transmission mechanism. We evaluate the effectiveness of the proposed scheme focusing on the on-chip buses of a microprocessor and by using the SPEC2000 benchmarks. The experimental results show that the proposed approach improves performance by 31.5% as compared to the original pessimistic approach. Furthermore, we employ a coding optimization to enhance the effectiveness of the proposed approach. We also show that the proposed scheme is an area-efficient approach to improving performance as compared to other crosstalk reduction schemes.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
EditorsG. Gielen, J. Figueras
Pages102-107
Number of pages6
Volume1
StatePublished - Jul 12 2004
EventProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris, France
Duration: Feb 16 2004Feb 20 2004

Other

OtherProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
CountryFrance
CityParis
Period2/16/042/20/04

Fingerprint

Crosstalk
Microprocessor chips
Clocks
Wire
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Li, L., Narayanan, V., Kandemir, M., & Irwin, M. J. (2004). A crosstalk aware interconnect with variable cycle transmission. In G. Gielen, & J. Figueras (Eds.), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 (Vol. 1, pp. 102-107)
Li, Lin ; Narayanan, Vijaykrishnan ; Kandemir, Mahmut ; Irwin, Mary Jane. / A crosstalk aware interconnect with variable cycle transmission. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. editor / G. Gielen ; J. Figueras. Vol. 1 2004. pp. 102-107
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Li, L, Narayanan, V, Kandemir, M & Irwin, MJ 2004, A crosstalk aware interconnect with variable cycle transmission. in G Gielen & J Figueras (eds), Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. vol. 1, pp. 102-107, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, France, 2/16/04.

A crosstalk aware interconnect with variable cycle transmission. / Li, Lin; Narayanan, Vijaykrishnan; Kandemir, Mahmut; Irwin, Mary Jane.

Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. ed. / G. Gielen; J. Figueras. Vol. 1 2004. p. 102-107.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - Crosstalk between wires, caused by increased capacitive coupling, is considered one of the major factors that affect the performance of interconnects such as buses. The data-dependent nature of crosstalk-induced delays necessitates bus cycle time to be designed for the worst case crosstalk. However, this pessimism incurs a significant performance penalty. Consequently, we propose a crosstalk aware interconnect that uses a faster clock and dynamically controls the number of cycles required for transmission based on the estimated delay of the data pattern to be transmitted. In order to accomplish this, we designed a crosstalk analyzer circuit that is incorporated into the sender side of the bus and support a variable cycle transmission mechanism. We evaluate the effectiveness of the proposed scheme focusing on the on-chip buses of a microprocessor and by using the SPEC2000 benchmarks. The experimental results show that the proposed approach improves performance by 31.5% as compared to the original pessimistic approach. Furthermore, we employ a coding optimization to enhance the effectiveness of the proposed approach. We also show that the proposed scheme is an area-efficient approach to improving performance as compared to other crosstalk reduction schemes.

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Li L, Narayanan V, Kandemir M, Irwin MJ. A crosstalk aware interconnect with variable cycle transmission. In Gielen G, Figueras J, editors, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04. Vol. 1. 2004. p. 102-107