A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays

Ching Yi Huang; Chian Wei Liu; Chun Yao Wang; Yung Chih Chen; Suman Datta; Vijaykrishnan Narayanan

doi:10.1109/ASPDAC.2015.7058991

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays

Ching Yi Huang, Chian Wei Liu, Chun Yao Wang, Yung Chih Chen, Suman Datta, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches were proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, no mapping approaches that consider the existence of defective nanowire segments were proposed. Thus, this paper presents the first defect-aware approach for mapping reconfigurable SET arrays. The experimental results show that our approach can successfully map the SET arrays with 20% width overhead on average in the presence of 5000 ppm defects.

Original language	English (US)
Title of host publication	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	118-123
Number of pages	6
ISBN (Electronic)	9781479977925
DOIs	https://doi.org/10.1109/ASPDAC.2015.7058991
State	Published - Mar 11 2015
Event	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan Duration: Jan 19 2015 → Jan 22 2015

Publication series

Name	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Country/Territory	Japan
City	Chiba
Period	1/19/15 → 1/22/15

All Science Journal Classification (ASJC) codes

Computer Science Applications
Electrical and Electronic Engineering
Control and Systems Engineering
Modeling and Simulation

Access to Document

10.1109/ASPDAC.2015.7058991

Cite this

Huang, C. Y., Liu, C. W., Wang, C. Y., Chen, Y. C., Datta, S., & Narayanan, V. (2015). A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 118-123). [7058991] (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058991

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title = "A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays",

abstract = "Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches were proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, no mapping approaches that consider the existence of defective nanowire segments were proposed. Thus, this paper presents the first defect-aware approach for mapping reconfigurable SET arrays. The experimental results show that our approach can successfully map the SET arrays with 20% width overhead on average in the presence of 5000 ppm defects.",

author = "Huang, {Ching Yi} and Liu, {Chian Wei} and Wang, {Chun Yao} and Chen, {Yung Chih} and Suman Datta and Vijaykrishnan Narayanan",

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Huang, CY, Liu, CW, Wang, CY, Chen, YC, Datta, S & Narayanan, V 2015, A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7058991, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 118-123, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 1/19/15. https://doi.org/10.1109/ASPDAC.2015.7058991

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. / Huang, Ching Yi; Liu, Chian Wei; Wang, Chun Yao et al.
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 118-123 7058991 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Liu, Chian Wei

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AU - Datta, Suman

AU - Narayanan, Vijaykrishnan

PY - 2015/3/11

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N2 - Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches were proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, no mapping approaches that consider the existence of defective nanowire segments were proposed. Thus, this paper presents the first defect-aware approach for mapping reconfigurable SET arrays. The experimental results show that our approach can successfully map the SET arrays with 20% width overhead on average in the presence of 5000 ppm defects.

AB - Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches were proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, no mapping approaches that consider the existence of defective nanowire segments were proposed. Thus, this paper presents the first defect-aware approach for mapping reconfigurable SET arrays. The experimental results show that our approach can successfully map the SET arrays with 20% width overhead on average in the presence of 5000 ppm defects.

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Huang CY, Liu CW, Wang CY, Chen YC, Datta S, Narayanan V. A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 118-123. 7058991. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). doi: 10.1109/ASPDAC.2015.7058991

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays

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