A design-space exploration tool for low-power DCT and IDCT hardware accelerators

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The discrete cosine transform (DCT) and its inverse (IDCT) are often used for image compression and decompression. Truncated-matrix multipliers offer reduced area, power and delay at the expense of increased computational error. This paper describes a software tool for design-space exploration of low-power DCT and IDCT hardware accelerators that use truncated-matrix multipliers. The tool has an interactive graphical user interface and is written entirely in Java. It can open image files, simulate compression and/or decompression, and display the processed image and error statistics.

Original languageEnglish (US)
Title of host publication2012 IEEE 16th International Symposium on Consumer Electronics, ISCE 2012
DOIs
StatePublished - Sep 26 2012
Event2012 IEEE 16th International Symposium on Consumer Electronics, ISCE 2012 - Harrisburg, PA, United States
Duration: Jun 4 2012Jun 6 2012

Publication series

NameDigest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)0747-668X

Other

Other2012 IEEE 16th International Symposium on Consumer Electronics, ISCE 2012
CountryUnited States
CityHarrisburg, PA
Period6/4/126/6/12

All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A design-space exploration tool for low-power DCT and IDCT hardware accelerators'. Together they form a unique fingerprint.

  • Cite this

    Walters, III, E. G. (2012). A design-space exploration tool for low-power DCT and IDCT hardware accelerators. In 2012 IEEE 16th International Symposium on Consumer Electronics, ISCE 2012 [6241736] (Digest of Technical Papers - IEEE International Conference on Consumer Electronics). https://doi.org/10.1109/ISCE.2012.6241736