A dual-VDD low power FPGA architecture

A. Gayasen, K. Lee, Vijaykrishnan Narayanan, Mahmut Kandemir, M. J. Irwin, T. Tuan

Research output: Contribution to journalArticle

42 Scopus citations


The continuing increase in FPGA size and complexity and the emergence of sub-100nm technology have made FPGA power consumption, both dynamic and static, an important design consideration. In this work, we propose a programmable dual-VDD architecture in which the supply voltage of the logic blocks and routing blocks are programmed to reduce power consumption by assigning low-VDD to non-critical paths in the design, while assigning high-VDD to the timing critical paths in the design to meet timing constraints. We evaluate the effectiveness of different VDD assignment algorithms and architectural implementations. Our experimental results show that reducing the supply voltage selectively to the non-critical paths provides significant power savings with minimal impact on performance. One of our VDD-assignment techniques provides an average power saving of 61% across different MCNC benchmarks.

Original languageEnglish (US)
Pages (from-to)145-157
Number of pages13
JournalLecture Notes in Computer Science
StatePublished - 2004

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

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    Gayasen, A., Lee, K., Narayanan, V., Kandemir, M., Irwin, M. J., & Tuan, T. (2004). A dual-VDD low power FPGA architecture. Lecture Notes in Computer Science, 3203, 145-157.