A generic and reconfigurable test paradigm using low-cost integrated poly-Si TFTs

Jing Li, Swaroop Ghosh, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

In this work, we propose a novel low power, process tolerant, generic and reconfigurable test structure to reduce the test cost, improve diagnosability and verifiability of complex VLSI systems. The test structure contains a variety of configurable design-for-test units designed with low cost Low Temperature Polycrystalline Silicon Thin Film Transistors (LTPS TFTs) that are fabricated on a separate substrate (e.g., polymer, glass etc). The proposed test circuits do not consume any silicon area because they can be integrated on the chip using 3-D technology. This reconfigurable test paradigm eliminates the need to re-design the BIST components that may vary from one processor generation to another.

Original languageEnglish (US)
Title of host publication2007 IEEE International Test Conference, ITC
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)1424411289, 9781424411283
DOIs
StatePublished - Jan 1 2007
Event2007 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: Oct 23 2007Oct 25 2007

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Other

Other2007 IEEE International Test Conference, ITC
CountryUnited States
CitySanta Clara, CA
Period10/23/0710/25/07

Fingerprint

Polysilicon
Paradigm
Built-in self test
Thin film transistors
Costs
Glass
Silicon
Networks (circuits)
Polymers
Substrates
Diagnosability
Thin-film Transistor
Temperature
3D
Chip
Eliminate
Substrate
Vary
Unit

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Li, J., Ghosh, S., & Roy, K. (2007). A generic and reconfigurable test paradigm using low-cost integrated poly-Si TFTs. In 2007 IEEE International Test Conference, ITC [4437622] (Proceedings - International Test Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TEST.2007.4437622
Li, Jing ; Ghosh, Swaroop ; Roy, Kaushik. / A generic and reconfigurable test paradigm using low-cost integrated poly-Si TFTs. 2007 IEEE International Test Conference, ITC. Institute of Electrical and Electronics Engineers Inc., 2007. (Proceedings - International Test Conference).
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Li, J, Ghosh, S & Roy, K 2007, A generic and reconfigurable test paradigm using low-cost integrated poly-Si TFTs. in 2007 IEEE International Test Conference, ITC., 4437622, Proceedings - International Test Conference, Institute of Electrical and Electronics Engineers Inc., 2007 IEEE International Test Conference, ITC, Santa Clara, CA, United States, 10/23/07. https://doi.org/10.1109/TEST.2007.4437622

A generic and reconfigurable test paradigm using low-cost integrated poly-Si TFTs. / Li, Jing; Ghosh, Swaroop; Roy, Kaushik.

2007 IEEE International Test Conference, ITC. Institute of Electrical and Electronics Engineers Inc., 2007. 4437622 (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Li J, Ghosh S, Roy K. A generic and reconfigurable test paradigm using low-cost integrated poly-Si TFTs. In 2007 IEEE International Test Conference, ITC. Institute of Electrical and Electronics Engineers Inc. 2007. 4437622. (Proceedings - International Test Conference). https://doi.org/10.1109/TEST.2007.4437622