A generic reconfigurable neural network architecture implemented as a network on chip

T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin, V. Srikantam

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Scopus citations

Abstract

Neural networks are widely used in pattern recognition, security applications and data manipulation. We propose a novel hardware architecture for a generic neural network, using Network on Chip (NoC) interconnect. The proposed architecture allows for expandability, mapping of more than one logical unit onto a single physical unit, and dynamic reconfiguration based on application-specific demands. Simulation results show that this architecture has significant performance benefits over existing architectures.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference
EditorsJ. Chickanosky, D. Ha, R. Auletta
Pages191-194
Number of pages4
StatePublished - Dec 1 2004
EventProceedings - IEEE International SOC Conference - Santa Clara, CA, United States
Duration: Sep 12 2004Sep 15 2004

Publication series

NameProceedings - IEEE International SOC Conference

Other

OtherProceedings - IEEE International SOC Conference
CountryUnited States
CitySanta Clara, CA
Period9/12/049/15/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Theocharides, T., Link, G., Vijaykrishnan, N., Irwin, M. J., & Srikantam, V. (2004). A generic reconfigurable neural network architecture implemented as a network on chip. In J. Chickanosky, D. Ha, & R. Auletta (Eds.), Proceedings - IEEE International SOC Conference (pp. 191-194). [TA1.3] (Proceedings - IEEE International SOC Conference).