Hardware-software codesign is a powerful technique that can be used to build complex systems. In this paper, we propose a compiler driven hardware-software codesign strategy that works at application level, aiming at facilitating algorithm architecture co-explorations. The proposed approach employs an intermediate code representation, called Loop Hierarchy Tree (LHT), to perform codesign exploration, and applies a branchand- bound search to find a hardware-software partitioning that minimizes execution latency under the given area constraints. We also developed fast cost estimation models for LHT and can be extended to handle codesign for more complex hybrid architectures. Experimental results show that our approach is successful in finding good solutions for the applications on thetarget codesign platform.