A heuristic for clock selection in high-level synthesis

J. Ramanujam, S. Deshpande, J. Hong, M. Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.

Original languageEnglish (US)
Title of host publicationProceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages414-419
Number of pages6
ISBN (Electronic)0769514413, 9780769514413
DOIs
StatePublished - Jan 1 2002
Event7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 - Bangalore, India
Duration: Jan 7 2002Jan 11 2002

Publication series

NameProceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Other

Other7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
CountryIndia
CityBangalore
Period1/7/021/11/02

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Ramanujam, J., Deshpande, S., Hong, J., & Kandemir, M. (2002). A heuristic for clock selection in high-level synthesis. In Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 (pp. 414-419). [994956] (Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2002.994956