A high-speed power and resolution adaptive flash analog-to-digital converter

Sunny Nahata, Kyusun Choi, Jincheol Yoo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

A high-speed and small-area power and resolution adaptive flash ADC is presented. The High-Speed Power and Resolution Adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference
EditorsJ. Chickanosky, D. Ha, R. Auletta
Pages33-36
Number of pages4
StatePublished - 2004
EventProceedings - IEEE International SOC Conference - Santa Clara, CA, United States
Duration: Sep 12 2004Sep 15 2004

Other

OtherProceedings - IEEE International SOC Conference
CountryUnited States
CitySanta Clara, CA
Period9/12/049/15/04

Fingerprint

Digital to analog conversion
Comparator circuits
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Nahata, S., Choi, K., & Yoo, J. (2004). A high-speed power and resolution adaptive flash analog-to-digital converter. In J. Chickanosky, D. Ha, & R. Auletta (Eds.), Proceedings - IEEE International SOC Conference (pp. 33-36)
Nahata, Sunny ; Choi, Kyusun ; Yoo, Jincheol. / A high-speed power and resolution adaptive flash analog-to-digital converter. Proceedings - IEEE International SOC Conference. editor / J. Chickanosky ; D. Ha ; R. Auletta. 2004. pp. 33-36
@inproceedings{2edf41f408914cffbd898914ebc77546,
title = "A high-speed power and resolution adaptive flash analog-to-digital converter",
abstract = "A high-speed and small-area power and resolution adaptive flash ADC is presented. The High-Speed Power and Resolution Adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.",
author = "Sunny Nahata and Kyusun Choi and Jincheol Yoo",
year = "2004",
language = "English (US)",
isbn = "0780384458",
pages = "33--36",
editor = "J. Chickanosky and D. Ha and R. Auletta",
booktitle = "Proceedings - IEEE International SOC Conference",

}

Nahata, S, Choi, K & Yoo, J 2004, A high-speed power and resolution adaptive flash analog-to-digital converter. in J Chickanosky, D Ha & R Auletta (eds), Proceedings - IEEE International SOC Conference. pp. 33-36, Proceedings - IEEE International SOC Conference, Santa Clara, CA, United States, 9/12/04.

A high-speed power and resolution adaptive flash analog-to-digital converter. / Nahata, Sunny; Choi, Kyusun; Yoo, Jincheol.

Proceedings - IEEE International SOC Conference. ed. / J. Chickanosky; D. Ha; R. Auletta. 2004. p. 33-36.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A high-speed power and resolution adaptive flash analog-to-digital converter

AU - Nahata, Sunny

AU - Choi, Kyusun

AU - Yoo, Jincheol

PY - 2004

Y1 - 2004

N2 - A high-speed and small-area power and resolution adaptive flash ADC is presented. The High-Speed Power and Resolution Adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.

AB - A high-speed and small-area power and resolution adaptive flash ADC is presented. The High-Speed Power and Resolution Adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.

UR - http://www.scopus.com/inward/record.url?scp=14844288073&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=14844288073&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:14844288073

SN - 0780384458

SP - 33

EP - 36

BT - Proceedings - IEEE International SOC Conference

A2 - Chickanosky, J.

A2 - Ha, D.

A2 - Auletta, R.

ER -

Nahata S, Choi K, Yoo J. A high-speed power and resolution adaptive flash analog-to-digital converter. In Chickanosky J, Ha D, Auletta R, editors, Proceedings - IEEE International SOC Conference. 2004. p. 33-36