Abstract
A high-speed and small-area power and resolution adaptive flash ADC is presented. The High-Speed Power and Resolution Adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International SOC Conference |
| Editors | J. Chickanosky, D. Ha, R. Auletta |
| Pages | 33-36 |
| Number of pages | 4 |
| State | Published - 2004 |
| Event | Proceedings - IEEE International SOC Conference - Santa Clara, CA, United States Duration: Sep 12 2004 → Sep 15 2004 |
Other
| Other | Proceedings - IEEE International SOC Conference |
|---|---|
| Country/Territory | United States |
| City | Santa Clara, CA |
| Period | 9/12/04 → 9/15/04 |
All Science Journal Classification (ASJC) codes
- Engineering(all)