A high-speed power and resolution adaptive flash analog-to-digital converter

Sunny Nahata; Kyusun Choi; Jincheol Yoo

A high-speed power and resolution adaptive flash analog-to-digital converter

Sunny Nahata, Kyusun Choi, Jincheol Yoo

School of Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Scopus citations

Abstract

A high-speed and small-area power and resolution adaptive flash ADC is presented. The High-Speed Power and Resolution Adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.

Original language	English (US)
Title of host publication	Proceedings - IEEE International SOC Conference
Editors	J. Chickanosky, D. Ha, R. Auletta
Pages	33-36
Number of pages	4
State	Published - 2004
Event	Proceedings - IEEE International SOC Conference - Santa Clara, CA, United States Duration: Sep 12 2004 → Sep 15 2004

Other

Other	Proceedings - IEEE International SOC Conference
Country/Territory	United States
City	Santa Clara, CA
Period	9/12/04 → 9/15/04

All Science Journal Classification (ASJC) codes

Engineering(all)

Cite this

@inproceedings{2edf41f408914cffbd898914ebc77546,

title = "A high-speed power and resolution adaptive flash analog-to-digital converter",

abstract = "A high-speed and small-area power and resolution adaptive flash ADC is presented. The High-Speed Power and Resolution Adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.",

author = "Sunny Nahata and Kyusun Choi and Jincheol Yoo",

year = "2004",

language = "English (US)",

isbn = "0780384458",

pages = "33--36",

editor = "J. Chickanosky and D. Ha and R. Auletta",

booktitle = "Proceedings - IEEE International SOC Conference",

note = "Proceedings - IEEE International SOC Conference ; Conference date: 12-09-2004 Through 15-09-2004",

}

TY - GEN

T1 - A high-speed power and resolution adaptive flash analog-to-digital converter

AU - Nahata, Sunny

AU - Choi, Kyusun

AU - Yoo, Jincheol

PY - 2004

Y1 - 2004

N2 - A high-speed and small-area power and resolution adaptive flash ADC is presented. The High-Speed Power and Resolution Adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.

AB - A high-speed and small-area power and resolution adaptive flash ADC is presented. The High-Speed Power and Resolution Adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.

UR - http://www.scopus.com/inward/record.url?scp=14844288073&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=14844288073&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:14844288073

SN - 0780384458

SP - 33

EP - 36

BT - Proceedings - IEEE International SOC Conference

A2 - Chickanosky, J.

A2 - Ha, D.

A2 - Auletta, R.

T2 - Proceedings - IEEE International SOC Conference

Y2 - 12 September 2004 through 15 September 2004

ER -

A high-speed power and resolution adaptive flash analog-to-digital converter

Abstract

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All Science Journal Classification (ASJC) codes

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