A high-speed power and resolution adaptive flash analog-to-digital converter

Sunny Nahata, Kyusun Choi, Jincheol Yoo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

A high-speed and small-area power and resolution adaptive flash ADC is presented. The High-Speed Power and Resolution Adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference
EditorsJ. Chickanosky, D. Ha, R. Auletta
Pages33-36
Number of pages4
StatePublished - 2004
EventProceedings - IEEE International SOC Conference - Santa Clara, CA, United States
Duration: Sep 12 2004Sep 15 2004

Other

OtherProceedings - IEEE International SOC Conference
CountryUnited States
CitySanta Clara, CA
Period9/12/049/15/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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