TY - GEN
T1 - A High-Voltage ASIC for Ultrasound Neuromodulation with a Piezoelectric Transducer
AU - Gougheri, Hesam Sadeghi
AU - Kiani, Mehdi
N1 - Funding Information:
This work was supported by the National Institutes of Health (NIH) and National Science Foundation (NSF) under Grants R21EY029424 and ECCS-1942839, respectively.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Effective and safe ultrasound neuromodulation has been demonstrated in animals and humans with often bulky off-the-shelf high-voltage (HV) drivers and ultrasound transducers. This brief presents an efficient HV ASIC for driving a piezoelectric transducer as the first step towards a small portable system. A design method is presented for finding the optimal switching frequency left(f-{p}right) and duty cycle (DC) of the HV class DE driver for a given piezoelectric transducer. The ASIC integrates inductive power management, clock recovery, delay cell, and level shifter circuits for creating optimal switching signals for the H V driver from an A C power carrier. The ASIC was fabricated in a 0.25 mu m HV BCD CMOS process and integrated with 2.7 MHz flat and 4.6 MHz curved single-element piezoelectric transducers. In measurements, the ASIC could apply 40 V peak-peak voltages across transducers with optimal fp and DC calculated from our model, generating up to 3 MPa ultrasound pressure outputs with as high as 91 % power efficiency.
AB - Effective and safe ultrasound neuromodulation has been demonstrated in animals and humans with often bulky off-the-shelf high-voltage (HV) drivers and ultrasound transducers. This brief presents an efficient HV ASIC for driving a piezoelectric transducer as the first step towards a small portable system. A design method is presented for finding the optimal switching frequency left(f-{p}right) and duty cycle (DC) of the HV class DE driver for a given piezoelectric transducer. The ASIC integrates inductive power management, clock recovery, delay cell, and level shifter circuits for creating optimal switching signals for the H V driver from an A C power carrier. The ASIC was fabricated in a 0.25 mu m HV BCD CMOS process and integrated with 2.7 MHz flat and 4.6 MHz curved single-element piezoelectric transducers. In measurements, the ASIC could apply 40 V peak-peak voltages across transducers with optimal fp and DC calculated from our model, generating up to 3 MPa ultrasound pressure outputs with as high as 91 % power efficiency.
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U2 - 10.1109/ISCAS48785.2022.9937761
DO - 10.1109/ISCAS48785.2022.9937761
M3 - Conference contribution
AN - SCOPUS:85142503648
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 951
EP - 955
BT - IEEE International Symposium on Circuits and Systems, ISCAS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Y2 - 27 May 2022 through 1 June 2022
ER -