A linear array processor with dynamic frequency clocking for image processing applications

N. Ranganathan, N. Vijaykrishnan, N. Bhavanishankar

Research output: Contribution to journalArticle

17 Scopus citations

Abstract

The need for high-performance image processing systems has led to the design and development of several application-specific parallel processing systems. In this paper, a SIMD linear array processor with dynamic frequency clocking is proposed for real-time image processing applications. The architecture uses a novel concept called dynamic frequency clocking which allows the processor to vary the clock frequency dynamically based on the operation being performed. A VLSI chip based on the proposed architecture has been designed and verified using the Cadence design tools. The chip will operate between 400 and 50 MHz based on the operation being performed. Several low-level image processing tasks have been mapped onto the architecture to evaluate the system performance and to demonstrate the effectiveness of the dynamic frequency clocking scheme.

Original languageEnglish (US)
Pages (from-to)435-445
Number of pages11
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume8
Issue number4
DOIs
StatePublished - Jan 1 1998

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All Science Journal Classification (ASJC) codes

  • Media Technology
  • Electrical and Electronic Engineering

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