A low latency router supporting adaptivity for on-chip interconnects

Jongman Kim, Donakook Park, T. Theocharides, N. Vijaykrishnan, Chita R. Das

Research output: Contribution to journalConference articlepeer-review

197 Scopus citations


The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip (NoC) have been proposed. The NoC routing algorithm significantly influences the performance and energy consumption of the chip. We propose a router architecture which utilizes adaptive routing while maintaining low latency. The two-stage pipelined architecture uses look ahead routing, speculative allocation, and optimal output path selection concurrently. The routing algorithm benefits from congestion-aware flow control, making better routing decisions. We simulate and evaluate the proposed architecture in terms of network latency and energy consumption. Our results indicate that the architecture is effective in balancing the performance and energy of NoC designs.

Original languageEnglish (US)
Article number34.2
Pages (from-to)559-564
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - 2005
Event42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States
Duration: Jun 13 2005Jun 17 2005

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering


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