A low-power phase change memory based hybrid cache architecture

Prasanth Mangalagiri, Aditya Yanamandra, Xie Yuan, N. Vijaykrishnan, Mary Jane Irwin, Karthik Sarpatwari, O. O.Awadel Karim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

53 Scopus citations

Abstract

Sub-threshold leakage in SRAM based cache memories is becoming a predominant source of power consumption in deep-submicron CMOS designs. Phase Change Random Access Memory (PRAM), a high density, fast access, non-volatile memory is being considered as a candidate for future universal memory technologies. In this paper, we investigate the architectural challenges in integrating a PRAM based memory into the conventional cache hierarchy. First, we develop PRAM cache delay and energy models. We then propose a hybrid PRAM architecture for L1 instruction caches on embedded processors. We also propose a PRAM based unified cache architecture for L2 caches on high-end microprocessors. Finally, we evaluate the proposed architectures, in terms of area, performance, and energy. The experimental results show that the PRAM based cache architectures achieve close to 80% reduction in the leakage energy consumption of a L1-L2 cache hierarchy.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2008
Subtitle of host publicationProceedings of the 2008 ACM Great Lakes Symposium on VLSI
Pages395-398
Number of pages4
DOIs
StatePublished - Dec 1 2008
EventGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL, United States
Duration: Mar 4 2008Mar 6 2008

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Other

OtherGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
CountryUnited States
CityOrlando, FL
Period3/4/083/6/08

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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