A memory-conscious code parallelization scheme

Xue Liping, Ozean Ozturk, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

While there have been considerable work in the last couple of years for architecting embedded chip multiprocessors, programming and compiler support required for them took relatively less attention. Our goal in this paper is to show that conventional compiler-directed code parallelization used in high performance computing is not very suitable for embedded chip multiprocessors where minimizing memory space requirements is an important issue. We propose and evaluate a novel memory-conscious loop parallelization strategy with the objective of minimizing the data memory requirements of processors. The proposed approach, which is formulated as a branch-and-bound problem, accomplishes its objective by being careful in selecting the loops to parallelize in a given loop nest.

Original languageEnglish (US)
Title of host publication2007 44th ACM/IEEE Design Automation Conference, DAC'07
Pages230-233
Number of pages4
DOIs
StatePublished - Aug 2 2007
Event2007 44th ACM/IEEE Design Automation Conference, DAC'07 - San Diego, CA, United States
Duration: Jun 4 2007Jun 8 2007

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other2007 44th ACM/IEEE Design Automation Conference, DAC'07
CountryUnited States
CitySan Diego, CA
Period6/4/076/8/07

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

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    Liping, X., Ozturk, O., & Kandemir, M. (2007). A memory-conscious code parallelization scheme. In 2007 44th ACM/IEEE Design Automation Conference, DAC'07 (pp. 230-233). [4261177] (Proceedings - Design Automation Conference). https://doi.org/10.1109/DAC.2007.375158