A monolithic-3D SRAM design with enhanced robustness and in-memory computation support

Srivatsa Srinivasa, Akshay Krishna Ramanathan, Xueqing Li, Wei Hao Chen, Fu Kuo Hsueh, Chih Chao Yang, Chang Hong Shen, Jia Min Shieh, Sumeet Gupta, Meng Fan Marvin Chang, Swaroop Ghosh, Jack Sampson, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

We present a novel 3D-SRAM cell using a Monolithic 3D integration (M3D-IC) technology for realizing both robustness and In-memory Boolean logic compute support. The proposed twolayer design makes use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, XNOR/XOR) without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes and evaluate the energy efficiency of our proposed design. Assist techniques improve SRAM read stability by 2.2x and increase the write margin by 17.6%, while staying within the SRAM footprint. By virtue of increased robustness, the cell enables seamless operation at lower supply voltages and thereby ensures energy efficiency. Energy Delay Product (EDP) reduces by 1.6x over standard 6T SRAM with a faster data access. Transistor placement and their biasing technique in layer-2 enables In-memory bitwise Boolean computation. When computing bulk In-memory operations, 6.5x energy savings is achieved as compared to computing outside the memory system.

Original languageEnglish (US)
Title of host publicationISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781450357043
DOIs
StatePublished - Jul 23 2018
Event23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018 - Bellevue, United States
Duration: Jul 23 2018Jul 25 2018

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018
CountryUnited States
CityBellevue
Period7/23/187/25/18

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Fingerprint Dive into the research topics of 'A monolithic-3D SRAM design with enhanced robustness and in-memory computation support'. Together they form a unique fingerprint.

Cite this