A monolithic-3D SRAM design with enhanced robustness and in-memory computation support

Srivatsa Srinivasa, Akshay Krishna Ramanathan, Xueqing Li, Wei Hao Chen, Fu Kuo Hsueh, Chih Chao Yang, Chang Hong Shen, Jia Min Shieh, Sumeet Kumar Gupta, Meng Fan Marvin Chang, Swaroop Ghosh, John Morgan Sampson, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

We present a novel 3D-SRAM cell using a Monolithic 3D integration (M3D-IC) technology for realizing both robustness and In-memory Boolean logic compute support. The proposed twolayer design makes use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, XNOR/XOR) without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes and evaluate the energy efficiency of our proposed design. Assist techniques improve SRAM read stability by 2.2x and increase the write margin by 17.6%, while staying within the SRAM footprint. By virtue of increased robustness, the cell enables seamless operation at lower supply voltages and thereby ensures energy efficiency. Energy Delay Product (EDP) reduces by 1.6x over standard 6T SRAM with a faster data access. Transistor placement and their biasing technique in layer-2 enables In-memory bitwise Boolean computation. When computing bulk In-memory operations, 6.5x energy savings is achieved as compared to computing outside the memory system.

Original languageEnglish (US)
Title of host publicationISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781450357043
DOIs
StatePublished - Jul 23 2018
Event23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018 - Bellevue, United States
Duration: Jul 23 2018Jul 25 2018

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018
CountryUnited States
CityBellevue
Period7/23/187/25/18

Fingerprint

Static random access storage
Data storage equipment
Energy efficiency
Transistors
Energy conservation
Electric potential

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Srinivasa, S., Ramanathan, A. K., Li, X., Chen, W. H., Hsueh, F. K., Yang, C. C., ... Narayanan, V. (2018). A monolithic-3D SRAM design with enhanced robustness and in-memory computation support. In ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design [a34] (Proceedings of the International Symposium on Low Power Electronics and Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3218603.3218645
Srinivasa, Srivatsa ; Ramanathan, Akshay Krishna ; Li, Xueqing ; Chen, Wei Hao ; Hsueh, Fu Kuo ; Yang, Chih Chao ; Shen, Chang Hong ; Shieh, Jia Min ; Gupta, Sumeet Kumar ; Chang, Meng Fan Marvin ; Ghosh, Swaroop ; Sampson, John Morgan ; Narayanan, Vijaykrishnan. / A monolithic-3D SRAM design with enhanced robustness and in-memory computation support. ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2018. (Proceedings of the International Symposium on Low Power Electronics and Design).
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title = "A monolithic-3D SRAM design with enhanced robustness and in-memory computation support",
abstract = "We present a novel 3D-SRAM cell using a Monolithic 3D integration (M3D-IC) technology for realizing both robustness and In-memory Boolean logic compute support. The proposed twolayer design makes use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, XNOR/XOR) without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes and evaluate the energy efficiency of our proposed design. Assist techniques improve SRAM read stability by 2.2x and increase the write margin by 17.6{\%}, while staying within the SRAM footprint. By virtue of increased robustness, the cell enables seamless operation at lower supply voltages and thereby ensures energy efficiency. Energy Delay Product (EDP) reduces by 1.6x over standard 6T SRAM with a faster data access. Transistor placement and their biasing technique in layer-2 enables In-memory bitwise Boolean computation. When computing bulk In-memory operations, 6.5x energy savings is achieved as compared to computing outside the memory system.",
author = "Srivatsa Srinivasa and Ramanathan, {Akshay Krishna} and Xueqing Li and Chen, {Wei Hao} and Hsueh, {Fu Kuo} and Yang, {Chih Chao} and Shen, {Chang Hong} and Shieh, {Jia Min} and Gupta, {Sumeet Kumar} and Chang, {Meng Fan Marvin} and Swaroop Ghosh and Sampson, {John Morgan} and Vijaykrishnan Narayanan",
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Srinivasa, S, Ramanathan, AK, Li, X, Chen, WH, Hsueh, FK, Yang, CC, Shen, CH, Shieh, JM, Gupta, SK, Chang, MFM, Ghosh, S, Sampson, JM & Narayanan, V 2018, A monolithic-3D SRAM design with enhanced robustness and in-memory computation support. in ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design., a34, Proceedings of the International Symposium on Low Power Electronics and Design, Institute of Electrical and Electronics Engineers Inc., 23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018, Bellevue, United States, 7/23/18. https://doi.org/10.1145/3218603.3218645

A monolithic-3D SRAM design with enhanced robustness and in-memory computation support. / Srinivasa, Srivatsa; Ramanathan, Akshay Krishna; Li, Xueqing; Chen, Wei Hao; Hsueh, Fu Kuo; Yang, Chih Chao; Shen, Chang Hong; Shieh, Jia Min; Gupta, Sumeet Kumar; Chang, Meng Fan Marvin; Ghosh, Swaroop; Sampson, John Morgan; Narayanan, Vijaykrishnan.

ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2018. a34 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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T1 - A monolithic-3D SRAM design with enhanced robustness and in-memory computation support

AU - Srinivasa, Srivatsa

AU - Ramanathan, Akshay Krishna

AU - Li, Xueqing

AU - Chen, Wei Hao

AU - Hsueh, Fu Kuo

AU - Yang, Chih Chao

AU - Shen, Chang Hong

AU - Shieh, Jia Min

AU - Gupta, Sumeet Kumar

AU - Chang, Meng Fan Marvin

AU - Ghosh, Swaroop

AU - Sampson, John Morgan

AU - Narayanan, Vijaykrishnan

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N2 - We present a novel 3D-SRAM cell using a Monolithic 3D integration (M3D-IC) technology for realizing both robustness and In-memory Boolean logic compute support. The proposed twolayer design makes use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, XNOR/XOR) without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes and evaluate the energy efficiency of our proposed design. Assist techniques improve SRAM read stability by 2.2x and increase the write margin by 17.6%, while staying within the SRAM footprint. By virtue of increased robustness, the cell enables seamless operation at lower supply voltages and thereby ensures energy efficiency. Energy Delay Product (EDP) reduces by 1.6x over standard 6T SRAM with a faster data access. Transistor placement and their biasing technique in layer-2 enables In-memory bitwise Boolean computation. When computing bulk In-memory operations, 6.5x energy savings is achieved as compared to computing outside the memory system.

AB - We present a novel 3D-SRAM cell using a Monolithic 3D integration (M3D-IC) technology for realizing both robustness and In-memory Boolean logic compute support. The proposed twolayer design makes use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, XNOR/XOR) without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes and evaluate the energy efficiency of our proposed design. Assist techniques improve SRAM read stability by 2.2x and increase the write margin by 17.6%, while staying within the SRAM footprint. By virtue of increased robustness, the cell enables seamless operation at lower supply voltages and thereby ensures energy efficiency. Energy Delay Product (EDP) reduces by 1.6x over standard 6T SRAM with a faster data access. Transistor placement and their biasing technique in layer-2 enables In-memory bitwise Boolean computation. When computing bulk In-memory operations, 6.5x energy savings is achieved as compared to computing outside the memory system.

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Srinivasa S, Ramanathan AK, Li X, Chen WH, Hsueh FK, Yang CC et al. A monolithic-3D SRAM design with enhanced robustness and in-memory computation support. In ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc. 2018. a34. (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/3218603.3218645