A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-κ gate-dielectric MOSFETs

M. Jagadesh Kumar, Vivek Venkataraman, Sumeet Kumar Gupta

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A grounded lamination gate (GLG) structure for high-κ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.

Original languageEnglish (US)
Pages (from-to)2578-2581
Number of pages4
JournalIEEE Transactions on Electron Devices
Volume53
Issue number10
DOIs
StatePublished - Dec 1 2006

Fingerprint

Gate dielectrics
Oxides
Capacitance
Plate metal
Threshold voltage
Permittivity
Fabrication

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kumar, M. Jagadesh ; Venkataraman, Vivek ; Gupta, Sumeet Kumar. / A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-κ gate-dielectric MOSFETs. In: IEEE Transactions on Electron Devices. 2006 ; Vol. 53, No. 10. pp. 2578-2581.
@article{a9b2ab0aa5a14c2e85d041e24a69f310,
title = "A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-κ gate-dielectric MOSFETs",
abstract = "A grounded lamination gate (GLG) structure for high-κ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.",
author = "Kumar, {M. Jagadesh} and Vivek Venkataraman and Gupta, {Sumeet Kumar}",
year = "2006",
month = "12",
day = "1",
doi = "10.1109/TED.2006.882268",
language = "English (US)",
volume = "53",
pages = "2578--2581",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-κ gate-dielectric MOSFETs. / Kumar, M. Jagadesh; Venkataraman, Vivek; Gupta, Sumeet Kumar.

In: IEEE Transactions on Electron Devices, Vol. 53, No. 10, 01.12.2006, p. 2578-2581.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-κ gate-dielectric MOSFETs

AU - Kumar, M. Jagadesh

AU - Venkataraman, Vivek

AU - Gupta, Sumeet Kumar

PY - 2006/12/1

Y1 - 2006/12/1

N2 - A grounded lamination gate (GLG) structure for high-κ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.

AB - A grounded lamination gate (GLG) structure for high-κ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.

UR - http://www.scopus.com/inward/record.url?scp=64349088966&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=64349088966&partnerID=8YFLogxK

U2 - 10.1109/TED.2006.882268

DO - 10.1109/TED.2006.882268

M3 - Article

AN - SCOPUS:64349088966

VL - 53

SP - 2578

EP - 2581

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 10

ER -