A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-κ gate-dielectric MOSFETs

M. Jagadesh Kumar, Vivek Venkataraman, Sumeet Kumar Gupta

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

A grounded lamination gate (GLG) structure for high-κ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.

Original languageEnglish (US)
Pages (from-to)2578-2581
Number of pages4
JournalIEEE Transactions on Electron Devices
Volume53
Issue number10
DOIs
StatePublished - Dec 1 2006

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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