A New Grounded Lamination Gate (GLG) SOI MOSFET for diminished fringe capacitance effects

M. Jagadesh Kumar, Vivek Venkataraman, Sumeet Kumar Gupta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new Grounded Lamination Gate (GLG) structure is proposed in which grounded metal film is deposited in the spacer region on both sides of the gate to prevent the fringing field lines emanating from the bottom of the gate electrode from entering the source/drain regions. The variation of threshold voltage with gate dielectric permittivity is obtained for both the GLG and the conventional SOI MOSFETs using MEDICI. We demonstrate that the application of grounded lamination gate (GLG) structure is very effective in controlling the threshold voltage roll-off even for high gate dielectric permittivities.

Original languageEnglish (US)
Title of host publication2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
Pages709-712
Number of pages4
StatePublished - Dec 8 2006
Event2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings - Boston, MA, United States
Duration: May 7 2006May 11 2006

Publication series

Name2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
Volume1

Other

Other2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
CountryUnited States
CityBoston, MA
Period5/7/065/11/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Jagadesh Kumar, M., Venkataraman, V., & Gupta, S. K. (2006). A New Grounded Lamination Gate (GLG) SOI MOSFET for diminished fringe capacitance effects. In 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings (pp. 709-712). (2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings; Vol. 1).