TY - JOUR
T1 - A nonlinear lattice for high-amplitude picosecond pulse generation in CMOS
AU - Lee, Wooram
AU - Adnan, Muhammad
AU - Momeni, Omeed
AU - Afshari, Ehsan
N1 - Funding Information:
Manuscript received May 27, 2011; revised November 11, 2011; accepted November 18, 2011. Date of publication January 16, 2012; date of current version February 03, 2012. This work was supported by the C2S2 Focus Center, one of six research centers funded under the Focus Center Research Program (FCRP), a Semiconductor Research Corporation entity. The work of W. Lee is supported by Samsung fellowship and IEEE Solid-State Circuits Society predoctoral fellowship.
PY - 2012/2
Y1 - 2012/2
N2 - In this paper, we study an electrical nonlinear medium consisting of voltage-dependent capacitors and inductors to generate sharp pulses from a lower frequency sinusoid. First, we analyze the optimum conditions for maximum harmonic generation in a uniform nonlinear line. Next, we extend the nonlinear line to a two-dimensional nonlinear lattice that is compatible with CMOS technology. Compared with the nonlinear line, the lattice relies on spatial power combining, higher cut-off frequency, and nonlinear wave interaction to enhance the pulse amplitude and sharpness. To show the feasibility of this method, we implement the first CMOS nonlinear lattice in a 0.13-μm CMOS process, and successfully demonstrate 2.7-V pp, 6.3-ps pulses from a 22-GHz input signal.
AB - In this paper, we study an electrical nonlinear medium consisting of voltage-dependent capacitors and inductors to generate sharp pulses from a lower frequency sinusoid. First, we analyze the optimum conditions for maximum harmonic generation in a uniform nonlinear line. Next, we extend the nonlinear line to a two-dimensional nonlinear lattice that is compatible with CMOS technology. Compared with the nonlinear line, the lattice relies on spatial power combining, higher cut-off frequency, and nonlinear wave interaction to enhance the pulse amplitude and sharpness. To show the feasibility of this method, we implement the first CMOS nonlinear lattice in a 0.13-μm CMOS process, and successfully demonstrate 2.7-V pp, 6.3-ps pulses from a 22-GHz input signal.
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U2 - 10.1109/TMTT.2011.2178255
DO - 10.1109/TMTT.2011.2178255
M3 - Article
AN - SCOPUS:84862779809
SN - 0018-9480
VL - 60
SP - 370
EP - 380
JO - IRE Transactions on Microwave Theory and Techniques
JF - IRE Transactions on Microwave Theory and Techniques
IS - 2
M1 - 6132441
ER -