A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points

A. Raychowdhury, Swaroop Ghosh, S. Bhunia, D. Ghosh, K. Roy

Research output: Contribution to conferencePaper

5 Scopus citations

Abstract

We propose a delay fault testing methodology using on-chip delay measurement hardware. We have designed a process-tolerant, low-overhead delay measurement hardware and developed an algorithm to judiciously insert the hardware at internal nodes of logic blocks. Experimental results for a set of ISCAS89 benchmarks show up to 16.9% improvement in transition fault coverage and up to 10.5% increase in the number of detected faults for segment delay fault model, with fixed test length. The reduction in test length is up to 59% for transition fault, with fixed target coverage. The delay and area overhead due to additional DFT logic is limited to 2% and 4% respectively.

Original languageEnglish (US)
Pages108-113
Number of pages6
DOIs
StatePublished - Dec 1 2005
Event10th European Test Symposium, ETS 2005 - Tallinn, Estonia
Duration: May 22 2005May 25 2005

Other

Other10th European Test Symposium, ETS 2005
CountryEstonia
CityTallinn
Period5/22/055/25/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Raychowdhury, A., Ghosh, S., Bhunia, S., Ghosh, D., & Roy, K. (2005). A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points. 108-113. Paper presented at 10th European Test Symposium, ETS 2005, Tallinn, Estonia. https://doi.org/10.1109/ETS.2005.2