A novel on-chip delay measurement hardware for efficient speed-binning

A. Raychowdhury, Swaroop Ghosh, K. Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

27 Scopus citations

Abstract

With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spectrum. Consequently, speed binning of the high performance VLSI chips is essential and it costs significant amount of test application time. Further, the knowledge of the actual delay in the critical path of the circuit enables efficient use of typical low power methodologies e.g., voltage scaling, adaptive body biasing etc. In this paper, we have proposed a novel on-chip, low overhead and process tolerant delay measurement circuit which can estimate the critical path delay in a single clock period. This has the advantage of efficient on-chip speed binning.

Original languageEnglish (US)
Title of host publicationProceedings - 11th IEEE International On-Line Testing Symposium, IOLTS 2005
Pages287-292
Number of pages6
DOIs
StatePublished - Dec 1 2005
Event11th IEEE International On-Line Testing Symposium, IOLTS 2005 - French Riviera, France
Duration: Jul 6 2005Jul 8 2005

Publication series

NameProceedings - 11th IEEE International On-Line Testing Symposium, IOLTS 2005
Volume2005

Other

Other11th IEEE International On-Line Testing Symposium, IOLTS 2005
CountryFrance
CityFrench Riviera
Period7/6/057/8/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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