A novel Si-tunnel FET based SRAM design for ultra low-power 0.3V V DD applications

J. Singh, K. Ramakrishnan, S. Mookerjea, S. Datta, N. Vijaykrishnan, D. Pradhan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

67 Scopus citations

Abstract

Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6T SRAM cells. To overcome this limitation, 7T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6T SRAM design using Si-TFETs for reliable operation with low leakage at ultra low voltages. We also demonstrate that a functional 6T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using proposed design when compared with the 7T TFET SRAM cell. We achieve a leakage reduction improvement of 700X and 1600X over traditional CMOS SRAM designs at VDD of 0.3V and 0.5V respectively which makes it suitable for use at ultra-low power applications.

Original languageEnglish (US)
Title of host publication2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages181-186
Number of pages6
DOIs
StatePublished - Apr 28 2010
Event2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China
Duration: Jan 18 2010Jan 21 2010

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
CountryTaiwan, Province of China
CityTaipei
Period1/18/101/21/10

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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