A parallel architecture for hardware face detection

T. Theocharides, N. Vijaykrishnan, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

52 Scopus citations

Abstract

Face detection is a very important application in the field of machine vision. In this paper, we present a scalable parallel architecture which performs face detection using the AdaBoost algorithm. Experimental results show that the proposed architecture can detect faces with the same accuracy as the software implementation, on real-time video at a frame rate of 52 frames per second.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Pages452-453
Number of pages2
DOIs
StatePublished - Oct 9 2006
EventIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 - Klarlsruhe, Germany
Duration: Mar 2 2006Mar 3 2006

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Volume2006

Other

OtherIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
CountryGermany
CityKlarlsruhe
Period3/2/063/3/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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