A parallel state assignment algorithm for finite state machines

David A. Bader, Kamesh Madduri

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

This paper summarizes the design and implementation of a parallel algorithm for state assignment of large Finite State Machines (FSMs). High performance CAD tools are necessary to overcome the computational complexity involved in the optimization of large sequential circuits. FSMs constitute an important class of logic circuits, and state assignment is one of the key steps in combinational logic optimization. The SMP-based parallel algorithm - based on the sequential program JEDI targeting multilevel logic implementation - scales nearly linearly with the number of processors for FSMs of varying problem sizes chosen from standard benchmark suites while attaining quality of results comparable to the best sequential algorithms.

Original languageEnglish (US)
Pages (from-to)297-308
Number of pages12
JournalLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3296
StatePublished - Dec 1 2004

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State assignment
Finite automata
State Machine
Assignment
Logic
Parallel algorithms
Parallel Algorithms
Sequential circuits
Optimization
Sequential Algorithm
Logic circuits
Computational complexity
Computer aided design
Computational Complexity
High Performance
Linearly
Benchmark
Necessary

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

Cite this

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