A power and resolution adaptive flash analog-to-digital converter

Jincheol Yoo, Daegyu Lee, Kyusun Choi, Jongsoo Kim

Research output: Contribution to conferencePaper

29 Scopus citations

Abstract

A new power and resolution adaptive flash ADC, named PRA-ADC, is proposed. The PRA-ADC enables exponential power reduction with linear resolution reduction. Unused parallel voltage comparators are switched to standby mode. The voltage comparators consume only the leakage power during the standby mode. The PRA-ADC, capable of operating at 5-bit, 6-bit, 7-bit, and 8-bit precision, dissipates 69 mW at 5-bit and 435 mW at 8-bit. The PRA-ADC was designed and simulated with 0.18 μm CMOS technology. The PRA-ADC design is applicable to RD portable communication devices, allowing tighter management of power and efficiency.

Original languageEnglish (US)
Pages233-236
Number of pages4
StatePublished - Dec 1 2002
EventProceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States
Duration: Aug 12 2002Aug 14 2002

Other

OtherProceedings of the 2002 International Symposium on Low Power Electronics and Design
CountryUnited States
CityMonterey, CA
Period8/12/028/14/02

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Yoo, J., Lee, D., Choi, K., & Kim, J. (2002). A power and resolution adaptive flash analog-to-digital converter. 233-236. Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.