A power-efficient hybrid architecture design for image recognition using CNNs

Jinhang Choi, Srivatsa Srinivasa, Yasuki Tanabe, John Morgan Sampson, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Convolutional Neural Networks (CNNs) are proving to be highly effective in vision recognition systems. However, it is a challenge to use them in real-Time embedded systems because of their requirements for computation-intensive operations and high memory bandwidth. This paper proposes a power-efficient CNN architecture that has a pipelined streaming accelerator coupled to 4,096 SIMD Processing Elements. We reduce memory bandwidth via hierarchical intermediate data buffering and batch processing on the chip. As a result, we achieve high power-efficiency: Our proposed design processes 2,175 regions/second when operating at 500MHz with a power budget less than 7.5 Watts.

Original languageEnglish (US)
Title of host publicationProceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
PublisherIEEE Computer Society
Pages22-27
Number of pages6
ISBN (Print)9781538670996
DOIs
StatePublished - Aug 7 2018
Event17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018 - Hong Kong, Hong Kong
Duration: Jul 9 2018Jul 11 2018

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2018-July
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Other

Other17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
CountryHong Kong
CityHong Kong
Period7/9/187/11/18

Fingerprint

Image recognition
Neural networks
Bandwidth
Data storage equipment
Real time systems
Network architecture
Embedded systems
Particle accelerators
Processing

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Choi, J., Srinivasa, S., Tanabe, Y., Sampson, J. M., & Narayanan, V. (2018). A power-efficient hybrid architecture design for image recognition using CNNs. In Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018 (pp. 22-27). [8429336] (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2018-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2018.00015
Choi, Jinhang ; Srinivasa, Srivatsa ; Tanabe, Yasuki ; Sampson, John Morgan ; Narayanan, Vijaykrishnan. / A power-efficient hybrid architecture design for image recognition using CNNs. Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018. IEEE Computer Society, 2018. pp. 22-27 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI).
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abstract = "Convolutional Neural Networks (CNNs) are proving to be highly effective in vision recognition systems. However, it is a challenge to use them in real-Time embedded systems because of their requirements for computation-intensive operations and high memory bandwidth. This paper proposes a power-efficient CNN architecture that has a pipelined streaming accelerator coupled to 4,096 SIMD Processing Elements. We reduce memory bandwidth via hierarchical intermediate data buffering and batch processing on the chip. As a result, we achieve high power-efficiency: Our proposed design processes 2,175 regions/second when operating at 500MHz with a power budget less than 7.5 Watts.",
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Choi, J, Srinivasa, S, Tanabe, Y, Sampson, JM & Narayanan, V 2018, A power-efficient hybrid architecture design for image recognition using CNNs. in Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018., 8429336, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2018-July, IEEE Computer Society, pp. 22-27, 17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, Hong Kong, 7/9/18. https://doi.org/10.1109/ISVLSI.2018.00015

A power-efficient hybrid architecture design for image recognition using CNNs. / Choi, Jinhang; Srinivasa, Srivatsa; Tanabe, Yasuki; Sampson, John Morgan; Narayanan, Vijaykrishnan.

Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018. IEEE Computer Society, 2018. p. 22-27 8429336 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2018-July).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Choi J, Srinivasa S, Tanabe Y, Sampson JM, Narayanan V. A power-efficient hybrid architecture design for image recognition using CNNs. In Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018. IEEE Computer Society. 2018. p. 22-27. 8429336. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). https://doi.org/10.1109/ISVLSI.2018.00015