A process scheduler-based approach to NoC power management

F. Li, G. Chen, M. Kandemir, O. Ozturk, M. Karakoy, R. Ramanarayanan, B. Vaidyanathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Increasing use of on-chip networks as communication infrastructure in both high performance and low end computing makes it important to consider their power consumption. Several previously proposed approaches to power management in the context of NoCs (network-on-chips) are either pure hardware based or focus exclusively on a single application execution scenario. This paper makes two major contributions. First, it proposes a software-based proactive on-chip network power management scheme that operates under a given process scheduler. Second, it presents a power-aware process scheduling strategy, with the goal of maximizing power savings when we have multiple applications in the system. The paper also evaluates the proposed schemes under the different execution scenarios in the context of NoCs based on a two-dimensional mesh topology and compares them to each other as well as to a previouslyproposed hardware-based network power management scheme. Our experimental evaluation using six data-intensive applications shows that the proposed software based approach is competitive with the hardware based scheme. Also, we found that the power aware scheduling brings significant energy savings.

Original languageEnglish (US)
Title of host publicationProceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
Pages77-82
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07 - Bangalore, India
Duration: Jan 6 2007Jan 10 2007

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Other

Other20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
CountryIndia
CityBangalore
Period1/6/071/10/07

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A process scheduler-based approach to NoC power management'. Together they form a unique fingerprint.

Cite this