TY - GEN
T1 - A Pyramid-Type (PT) Multilevel Converter Topology
AU - Dargahi, Vahid
AU - Corzine, Keith
AU - Sadigh, Arash Khoshkbar
N1 - Publisher Copyright:
© 2020 IEEE.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2020/10/11
Y1 - 2020/10/11
N2 - This paper proposes a Pyramid-Type (PT) topology for multilevel power converters. The phase-leg of a PT-structure is comprised of half-bridge modules, as the main power electronics building blocks (PEBBs), that are connected in a pyramid form. The proposed PT-arrangement is primarily used to interconnect and tie the distinct and/or same types of 2-level and/or multilevel inverters together. The PEBBs are realized by the soft-switching low-frequency semiconductor devices such that the two switches of each half-bridge module turn on concurrently during voltage-level transitions. This is achieved through elimination of switching dead-time, and including an overlap into gate signals. This results in zero-voltage-switching (ZVS) or zero-current-switching (ZCS) phenomena for switches within the PEBBs. The utilization of PT-topology for interconnection of converters leads to new configurations. This paper reviews the PT-based derived topologies, and explores the advantages. For instance, a 3-level inverter topology, as the simplest structure, is investigated in this paper. The PT-topology is verified using the experimental results obtained from the prototype of a 3-level inverter formed by interconnection of two 2-level inverters via one PEBB.
AB - This paper proposes a Pyramid-Type (PT) topology for multilevel power converters. The phase-leg of a PT-structure is comprised of half-bridge modules, as the main power electronics building blocks (PEBBs), that are connected in a pyramid form. The proposed PT-arrangement is primarily used to interconnect and tie the distinct and/or same types of 2-level and/or multilevel inverters together. The PEBBs are realized by the soft-switching low-frequency semiconductor devices such that the two switches of each half-bridge module turn on concurrently during voltage-level transitions. This is achieved through elimination of switching dead-time, and including an overlap into gate signals. This results in zero-voltage-switching (ZVS) or zero-current-switching (ZCS) phenomena for switches within the PEBBs. The utilization of PT-topology for interconnection of converters leads to new configurations. This paper reviews the PT-based derived topologies, and explores the advantages. For instance, a 3-level inverter topology, as the simplest structure, is investigated in this paper. The PT-topology is verified using the experimental results obtained from the prototype of a 3-level inverter formed by interconnection of two 2-level inverters via one PEBB.
UR - http://www.scopus.com/inward/record.url?scp=85097157224&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85097157224&partnerID=8YFLogxK
U2 - 10.1109/ECCE44975.2020.9236255
DO - 10.1109/ECCE44975.2020.9236255
M3 - Conference contribution
AN - SCOPUS:85097157224
T3 - ECCE 2020 - IEEE Energy Conversion Congress and Exposition
SP - 3926
EP - 3933
BT - ECCE 2020 - IEEE Energy Conversion Congress and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 12th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2020
Y2 - 11 October 2020 through 15 October 2020
ER -