A rapid prototyping of FPGA-based duobinary transmitter/receiver for high speed electrical backplane transmission

Ashraf Umar, Aldo Morales, Sedig Agili, Mike Resso, Marcel Christoph Welpot

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Backplanes communication channels always have a distorting effect on the signals being passed from transmitter to receiver. Much effort research is being devoted on finding ways to reduce this distortion. This work focuses in rapid prototyping of a duobinary transmitter/receiver using a Field Programmable Gate Array. The transmitter comprises a precoder to prevent error propagation, a binary to duobinary encoder and a transmit filter. The signal is passed through a backplane channel and the channel output is equalized using a Least Mean Square filter. The system is modeled in Simulink and then the hardware description language code is generated from the model. Initial results show good eye diagram scopes which are placed at appropriate locations within the model to observe the signal at various points.

Original languageEnglish (US)
Title of host publicationDesignCon 2013
Subtitle of host publicationWhere Chipheads Connect
Pages197-209
Number of pages13
Publication statusPublished - Sep 16 2013
EventDesignCon 2013: Where Chipheads Connect - Santa Clara, CA, United States
Duration: Jan 28 2013Jan 31 2013

Publication series

NameDesignCon 2013: Where Chipheads Connect
Volume1

Other

OtherDesignCon 2013: Where Chipheads Connect
CountryUnited States
CitySanta Clara, CA
Period1/28/131/31/13

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Umar, A., Morales, A., Agili, S., Resso, M., & Welpot, M. C. (2013). A rapid prototyping of FPGA-based duobinary transmitter/receiver for high speed electrical backplane transmission. In DesignCon 2013: Where Chipheads Connect (pp. 197-209). (DesignCon 2013: Where Chipheads Connect; Vol. 1).