A reconfigurable low-power BDD logic architecture using ferroelectric single-electron transistors

Lu Liu, Xueqing Li, Vijaykrishnan Narayanan, Suman Datta

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

This paper presents ferroelectric single-electron transistors (SETs) with tunable tunnel barriers and their application in a reconfigurable binary decision diagram (BDD) logic architecture. In this experimental demonstration, the SETs can be programmed into short, open, and Coulomb blockade modes to construct the BDD fabric. We experimentally demonstrate the decision node, consisting of two SETs, with robust path switching characteristics. Harnessing such programmability and path switching features, a nonvolatile reconfigurable low-power BDD logic is achieved. A ferroelectric dielectric-based split gate configuration and a differential biasing scheme are utilized to share the programming resources and reduce the energy consumption. Peripheral interface circuits are designed to recover the output signal swing for cascaded BDD logic demonstration and to provide noise immunity. The simulation shows that with sufficient circuitry complexity or a latched dynamic CMOS interface, the proposed BDD architecture achieves higher power efficiency than CMOS at the same throughput delay.

Original languageEnglish (US)
Article number7035087
Pages (from-to)1052-1057
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume62
Issue number3
DOIs
StatePublished - Jan 1 2015

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Single electron transistors
Binary decision diagrams
Ferroelectric materials
Demonstrations
Coulomb blockade
Tunnels
Energy utilization
Throughput
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

@article{8aca9d83b74b4811858e4a5ec132251f,
title = "A reconfigurable low-power BDD logic architecture using ferroelectric single-electron transistors",
abstract = "This paper presents ferroelectric single-electron transistors (SETs) with tunable tunnel barriers and their application in a reconfigurable binary decision diagram (BDD) logic architecture. In this experimental demonstration, the SETs can be programmed into short, open, and Coulomb blockade modes to construct the BDD fabric. We experimentally demonstrate the decision node, consisting of two SETs, with robust path switching characteristics. Harnessing such programmability and path switching features, a nonvolatile reconfigurable low-power BDD logic is achieved. A ferroelectric dielectric-based split gate configuration and a differential biasing scheme are utilized to share the programming resources and reduce the energy consumption. Peripheral interface circuits are designed to recover the output signal swing for cascaded BDD logic demonstration and to provide noise immunity. The simulation shows that with sufficient circuitry complexity or a latched dynamic CMOS interface, the proposed BDD architecture achieves higher power efficiency than CMOS at the same throughput delay.",
author = "Lu Liu and Xueqing Li and Vijaykrishnan Narayanan and Suman Datta",
year = "2015",
month = "1",
day = "1",
doi = "10.1109/TED.2015.2395252",
language = "English (US)",
volume = "62",
pages = "1052--1057",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

A reconfigurable low-power BDD logic architecture using ferroelectric single-electron transistors. / Liu, Lu; Li, Xueqing; Narayanan, Vijaykrishnan; Datta, Suman.

In: IEEE Transactions on Electron Devices, Vol. 62, No. 3, 7035087, 01.01.2015, p. 1052-1057.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A reconfigurable low-power BDD logic architecture using ferroelectric single-electron transistors

AU - Liu, Lu

AU - Li, Xueqing

AU - Narayanan, Vijaykrishnan

AU - Datta, Suman

PY - 2015/1/1

Y1 - 2015/1/1

N2 - This paper presents ferroelectric single-electron transistors (SETs) with tunable tunnel barriers and their application in a reconfigurable binary decision diagram (BDD) logic architecture. In this experimental demonstration, the SETs can be programmed into short, open, and Coulomb blockade modes to construct the BDD fabric. We experimentally demonstrate the decision node, consisting of two SETs, with robust path switching characteristics. Harnessing such programmability and path switching features, a nonvolatile reconfigurable low-power BDD logic is achieved. A ferroelectric dielectric-based split gate configuration and a differential biasing scheme are utilized to share the programming resources and reduce the energy consumption. Peripheral interface circuits are designed to recover the output signal swing for cascaded BDD logic demonstration and to provide noise immunity. The simulation shows that with sufficient circuitry complexity or a latched dynamic CMOS interface, the proposed BDD architecture achieves higher power efficiency than CMOS at the same throughput delay.

AB - This paper presents ferroelectric single-electron transistors (SETs) with tunable tunnel barriers and their application in a reconfigurable binary decision diagram (BDD) logic architecture. In this experimental demonstration, the SETs can be programmed into short, open, and Coulomb blockade modes to construct the BDD fabric. We experimentally demonstrate the decision node, consisting of two SETs, with robust path switching characteristics. Harnessing such programmability and path switching features, a nonvolatile reconfigurable low-power BDD logic is achieved. A ferroelectric dielectric-based split gate configuration and a differential biasing scheme are utilized to share the programming resources and reduce the energy consumption. Peripheral interface circuits are designed to recover the output signal swing for cascaded BDD logic demonstration and to provide noise immunity. The simulation shows that with sufficient circuitry complexity or a latched dynamic CMOS interface, the proposed BDD architecture achieves higher power efficiency than CMOS at the same throughput delay.

UR - http://www.scopus.com/inward/record.url?scp=85027941865&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85027941865&partnerID=8YFLogxK

U2 - 10.1109/TED.2015.2395252

DO - 10.1109/TED.2015.2395252

M3 - Article

VL - 62

SP - 1052

EP - 1057

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 3

M1 - 7035087

ER -