A scalable bandwidth aware architecture for connected component labeling

Vikram Sampath Kumar, Kevin Irick, Ahmed Al Maashri, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component Labeling architecture that includes a scalable processor that can be tuned to match the I/O bandwidth available in modern embedded computing platforms.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
Pages116-121
Number of pages6
DOIs
StatePublished - 2010
EventIEEE Annual Symposium on VLSI, ISVLSI 2010 - Lixouri, Kefalonia, Greece
Duration: Jul 5 2010Jul 7 2010

Other

OtherIEEE Annual Symposium on VLSI, ISVLSI 2010
CountryGreece
CityLixouri, Kefalonia
Period7/5/107/7/10

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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