A steep-slope tunnel FET based SAR analog-to-digital converter

Moon Seok Kim, Huichu Liu, Xueqing Li, Suman Datta, Vijaykrishnan Narayanan

Research output: Contribution to journalArticle

19 Citations (Scopus)

Abstract

This paper explores the energy efficiency advantage of a 6-bit III-V heterojunction tunnel field-effect transistor (HTFET) based successive-approximation register (SAR) analog-to-digital converter (ADC) with 20-nm gate length. Compared with the Silicon FinFET (Si FinFET) ADC, the HTFET SAR ADC achieves approximately 3 times power consumption reduction and 6 times size reduction. Signal-to-noise and distortion ratio is 31.4 dB for the HTFET SAR ADC, which is 2.81 dB higher than the Si FinFET ADC due to the decreased quantization noise rising from the high ON-current characteristic of HTFET at low supply voltage. The energy per conversion step for both HTFET and Si FinFET ADC designs are 0.43 and 1.65 fJ/conversion-step, respectively, at a fixed supply voltage of 0.30 V.

Original languageEnglish (US)
Article number6922528
Pages (from-to)3661-3667
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume61
Issue number11
DOIs
StatePublished - Nov 1 2014

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Digital to analog conversion
Field effect transistors
Tunnels
Heterojunctions
Silicon
Electric potential
Energy efficiency
Electric power utilization
FinFET

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kim, Moon Seok ; Liu, Huichu ; Li, Xueqing ; Datta, Suman ; Narayanan, Vijaykrishnan. / A steep-slope tunnel FET based SAR analog-to-digital converter. In: IEEE Transactions on Electron Devices. 2014 ; Vol. 61, No. 11. pp. 3661-3667.
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A steep-slope tunnel FET based SAR analog-to-digital converter. / Kim, Moon Seok; Liu, Huichu; Li, Xueqing; Datta, Suman; Narayanan, Vijaykrishnan.

In: IEEE Transactions on Electron Devices, Vol. 61, No. 11, 6922528, 01.11.2014, p. 3661-3667.

Research output: Contribution to journalArticle

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AB - This paper explores the energy efficiency advantage of a 6-bit III-V heterojunction tunnel field-effect transistor (HTFET) based successive-approximation register (SAR) analog-to-digital converter (ADC) with 20-nm gate length. Compared with the Silicon FinFET (Si FinFET) ADC, the HTFET SAR ADC achieves approximately 3 times power consumption reduction and 6 times size reduction. Signal-to-noise and distortion ratio is 31.4 dB for the HTFET SAR ADC, which is 2.81 dB higher than the Si FinFET ADC due to the decreased quantization noise rising from the high ON-current characteristic of HTFET at low supply voltage. The energy per conversion step for both HTFET and Si FinFET ADC designs are 0.43 and 1.65 fJ/conversion-step, respectively, at a fixed supply voltage of 0.30 V.

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